Abstract: A receiver of a signal communication apparatus; the apparatus having a transmitter for transmitting the signals, the receiver for receiving the signals and a galvanically isolated wireless interface interposed between the transmitter and the receiver and having a transmitting antenna and a receiving antenna. The receiver including a disturbance rejection circuit coupled to the receiving antenna and capable of compensating for the parasite currents flowing between the transmitting antenna and the receiving antenna at the potential variations between the input and output of the galvanic isolation interface.

Abstract: A copper interconnect structure has an intrinsic graphene cap for improving back end of line (BEOL) reliability of the interconnect by reducing time-dependent dielectric breakdown (TDDB) failure and providing resistance to electromigration. Carbon atoms are selectively deposited onto a copper layer of the interconnect structure by a deposition process to form a graphene cap. The graphene cap increases the activation energy of the copper, thus allowing for higher current density and improved resistance to electromigration of the copper. By depositing the graphene cap on the copper, the dielectric regions remain free of conductors and, thus, current leakage within the interlayer dielectric regions is reduced, thereby reducing TDDB failure and increasing the lifespan of the interconnect structure. The reduction of TDDB failure and improved resistance to electromigration improves BEOL reliability of the copper interconnect structure.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A method for searching a digital transmission having unknown carrier and symbol frequencies in a modulated reception signal, includes performing successive trials of several carrier and symbol frequencies, using decreasing values of the symbol frequency, demodulating the reception signal with the tried carrier frequency, filtering the demodulated signal in a band having a width corresponding to the currently tried symbol frequency, and producing samples of the filtered signal. For each currently tried symbol frequency, forming a complex indicator having a real component and an imaginary component established from the successive samples of the filtered signal such that they have cyclostationary properties and that one of the components tends to cancel when the other component tends towards a relative maximum, building the spectrum of the variation of the complex indicator, searching for a singular spike in the spectrum, and determining the real symbol frequency from the frequency of the spike.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

Abstract: A Schmitt trigger circuit includes a first inverter having an input coupled to an input terminal; a second inverter having an input coupled to the input terminal; a first transistor having a source coupled to VDD, a drain coupled to an output of the first inverter, and a gate coupled to an output terminal; a second transistor having a source coupled to ground, a drain coupled to an output of the second inverter, and a gate coupled to the output terminal; a third transistor having a source coupled to VDD, a drain coupled to the output terminal, and a gate coupled to the output of the first inverter; and a fourth transistor having a source coupled to ground, a drain coupled to the output terminal, and a gate coupled to the output of the second inverter.

Abstract: A touch screen capable of correctly identifying multiple touches employs multiple active line arrays oriented to provide multi-dimensional data. Three arrays of capacitance based active lines are each distinctly oriented to form a plurality of intersections. A first and second array are generally oriented perpendicularly while a third array is oriented to bisect the resulting matrix such that the active lines of the third array also intersect the existing vertices. As a result of a touch each active line array identifies the location of the touch from three distinct directions. Ambiguity from dual touch scenarios existing in dual array systems is removed by providing an additional reference.

Abstract: A processor system having a processor core, a plurality of modules connected to the processor core and configured to generate respective fault signals, and a fault managing unit connected to the processor core and to the plurality of modules. The fault managing unit is adapted to collect a first fault signal generated by a first module of the plurality of modules which is in a fault condition, analyze said collected first fault signal, and generate a first reaction signal to be selectively transmitted to said processor core and said first module.

Abstract: A process for electrically testing electronic devices includes connecting at least one electronic device to an automatic testing apparatus suitable for testing digital circuits, and sending, through the apparatus, control signals for electrically testing the electronic device. The process further includes electrically testing the electronic device through at least one reconfigurable digital interface connected to the apparatus through a dedicated digital communication channel and comprising a limited number of communication or connection lines strictly appointed to the exchange of the testing information. Response messages are sent from the electronic device to the apparatus through the digital communication channel in response to the control signals. The response messages contain mesaurements, failure information, and data.

Abstract: A method is provided for controlling a converter of the multiphase interleaving type. According to the method, there is detected when a change of the load applied to an output terminal of the converter occurs. All the phases of the converter are simultaneously turned off, and a driving interleaving phase shift is recovered so as to restart a normal operation of the converter. A controller for carrying out such a method is also provided.

Abstract: An example method for writing and reading data in electrically erasable and programmable nonvolatile memory (EEPROM) cells may include writing, in erased blocks of a first memory zone, data each having a logical address defined in relation to a virtual memory; writing, in a second memory zone, metadata structures associated with the data present in the first memory zone, configuring, in a volatile memory zone, for each logical address of a data stored in the first memory zone, addresses of metadata structures comprising the logical address, reading the look-up table and then reading metadata structures that the look-up table designates, to find, from the logical address of a data, an address in the first memory zone of a block containing a valid data having the logical address.

Abstract: Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames.

Abstract: In an MIS structure a field plate electrode is incorporated below a buried gate electrode by using an insulating oxide layer, which is formed concurrently with the gate dielectric layer. In order to obtain superior dynamic behavior and enhanced dielectric strength the oxidation behavior of the field plate electrode is modified, for instance by incorporating a desired high concentration of arsenic.

Abstract: A sensing circuit for use in a semiconductor memory device includes first and second conducting lines for conducting a bit signal to and from a memory cell. The circuit further includes a sense amplifier coupled to the first and second conducting lines for sensing a bit signal, a charge storing element for generating a predefined potential, and first and second switching element respectively coupled to the first and second conducting lines. The first and second switching elements are selectively controllable to connect the first and second conducting line to the charge storing element so as to induce the generated predefined voltage on the first or second conducting lines.

Abstract: A circuit for converting the state of a sensor into a signal interpretable by an electronic circuit, including: a comparator of the voltage level of an input terminal with respect to a reference level, the sensor being intended to be connected between a terminal of application of a first power supply voltage and the input terminal; a current-limiting element between said input terminal and the ground; and a switching element in series with the current source and intended to be controlled by a pulse train.

Abstract: An integrated circuit includes a saw-tooth generator including a saw tooth node configured to have a saw-tooth voltage generated thereon; and a first switch having a first end connected to the saw tooth node. The integrated circuit further includes a second switch coupled between an output node and an electrical ground, wherein the first switch and the second switch are configured to operate synchronously. A first current source is connected to the saw tooth node. A second current source is connected to the output node.

Abstract: A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.

Abstract: The mass of an object may be estimated based on intersection points of a representation of a surface in an image space with cubes defining the image space, the surface representing a surface of an object. The representation may be, for example, based on marching cubes. The mass may be estimated by estimating a mass contribution of a first set of cubes contained entirely within the representation of the surface, estimating a mass contribution of a second set of cubes having intersection points with the representation of the surface, and summing the estimated mass contribution of the first set of cubes and the estimated mass contribution of the second set of cubes. The object may be segmented from other portions of an image prior to estimating the mass of the object.