Abstract: Disclosed is a sensor apparatus comprising a plurality of pixels, a digital to analog converter for providing a ramp signal, A comparator for comparing the output level of each pixel to said ramp signal, and memory for storing the digital value that corresponds to said output level for each pixel, the sensor apparatus thereby converting the analog output level of each pixel to a digital value. The apparatus operates by providing an analog output that is sourced from the digital to analog converter used to provide said ramp signal.

Abstract: An image sensor may include a shared memory resource, which can be selectively used by a digital filter for image scaling or by a defect correction circuit.

Abstract: A self-coexistence window reservation protocol for a plurality of Wireless Regional Area Network (WRAN) cells operating in a WRAN over a plurality of channels includes a sequence of self-coexistence windows that uniquely identifies a transmission period for each WRAN cell. A self-coexistence window reservation protocol is included within the first packet of a Coexistence Beaconing Protocol period identifying when each WRAN cell associated with a particular channel will transmit. When not actively transmitting, a WRAN cells remains in a passive, receiving mode to accept data. As the transmissions of each WRAN cell operating on a particular channel are scheduled, contention for a transmission period is eliminated.

Abstract: Continuous time analogue/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analogue input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract: An image sensor may selectively produce an effect, such as simulating a night vision scope, by controlling existing hardware to vary anti-vignetting and gamma.

Abstract: A system for providing an assembler for a microprocessor has a file which contains data describing the instruction set of the microprocessor. A translation device for translating into machine language accesses the instruction set descriptors to constrain the machine code output of the assembler to conform to the architecture of the instruction set.

Abstract: A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits.

Abstract: A sensor array microchip apparatus includes a substrate and a lens positioned over the substrate. A plurality of radiation sensor elements are formed on the substrate in an array format and spatially separated from each other. The substrate further includes power supply circuitry (generating power for the radiation sensor elements) and processing circuitry (operable to control and process information from the radiation sensor elements). The power supply circuitry and said processing circuitry are positioned on the substrate within the array between two or more of the radiation sensor elements. The lens, in combination with the spatial separation of the radiation sensor elements in the array format, defines a relatively wide (30-80 degrees) field of regard for the sensor.

Abstract: A voltage booster device may include a plurality of multiplication stages arranged in a sequence so that an input terminal of each multiplication stage, with the exception of a first multiplication stage, is connected to an output terminal of a previous multiplication stage. Each multiplication stage may include pumping circuitry for accumulating an electric charge proportional to a pump voltage value of the multiplication stage. Each multiplication stage may also include a phase signal generating circuit for switching the multiplication stages between a transfer phase and a maintaining phase. In at least one of the stages, the pumping circuitry may include at least two series connected charge accumulators. A terminal may be shared between the charge accumulators and may be connected through biasing circuitry to an output terminal of a previous multiplication stage for forcing the charge accumulators within a threshold potential drop value.

Abstract: An integrated MEMS gyroscope, is provided with: at least a first driving mass driven with a first driving movement along a first axis upon biasing of an assembly of driving electrodes, the first driving movement generating at least one sensing movement, in the presence of rotations of the integrated MEMS gyroscope; and at least a second driving mass driven with a second driving movement along a second axis, transverse to the first axis, the second driving movement generating at least a respective sensing movement, in the presence of rotations of the integrated MEMS gyroscope. The integrated MEMS gyroscope is moreover provided with a first elastic coupling element, which elastically couples the first driving mass and the second driving mass in such a way as to couple the first driving movement to the second driving movement with a given ratio of movement.

Abstract: A power supply circuit capable of providing two regulated voltages based on a D.C. input voltage, including a boost converter and a buck-boost converter, the circuit including a single inductive element common to the boost and buck-boost converters.

Abstract: A radiation sensor includes first and second pixels with a radiation absorption filter positioned over the first pixel and an interference filter positioned over both the first and second pixels. The combined spectral response of the absorption filter and the first pixel has a first pixel pass-band and a first pixel stop-band. The spectral response of the interference filter has an interference filter pass-band which is substantially within the first pixel pass-band for radiation incident on the interference filter at a first angle of incidence, and substantially within the first pixel stop-band for radiation incident on the interference filter at a second angle of incidence greater than the first angle of incidence.

Abstract: A bulk acoustic wave resonator has an adjustable resonance frequency. A piezoelectric element is provided having first and second electrodes. A switching element is provided in the form of a MEMS structure which is deformable between a first and second position. The switching element forms an additional electrode that is selectively disposed on top of, and in contact with, one of the first and second electrodes. This causes a total thickness of the electrode of the resonator to be changed resulting in a modification of the resonance frequency of the resonator.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 ?m, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract: A device includes a positive power supply voltage node; and a first operational amplifier including a first input, a second input, and an output coupled to the second input. The device further includes a first resistor coupled between the second input of the first operational amplifier and the positive power supply voltage node; a second resistor coupled between the output of the first operational amplifier and an electrical ground, and is configured to receive a same current flowing through the first resistor; a second operational amplifier including a first input coupled to the second resistor, and an output coupled to an output node; and a third resistor coupled between the electrical ground and a second input of the second operational amplifier.

Abstract: A capacitive humidity sensor includes a first electrode, a humidity sensitive dielectric layer, and a second electrode. The humidity sensitive dielectric layer is between the first and the second electrodes. The humidity sensitive dielectric layer is etched at selected regions to form hollow regions between the first and second electrodes.

Abstract: The present disclosure is directed to a device and a method for achieving a precise capacitance of a capacitor. The method includes trimming a first capacitance of the capacitor to a second capacitance, the capacitor having a first conductive layer separated from a second conductive layer by a dielectric layer. Changing a first dielectric constant of the dielectric layer to a second dielectric constant, where the first dielectric constant corresponding to the first capacitance and the second dielectric constant corresponding to the second dielectric constant includes heating the dielectric layer above a threshold temperature for a time period. The heat is provided by either one of the plates of the capacitor or from a separate heater.

Abstract: A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.