Abstract: A method comprises providing a bottom electrode, depositing, on the bottom electrode, an active material comprising a first structural portion having an absorption peak at a UV wavelength, wherein such first structural portion is photo-activatable at such wavelength and which is constituted by monomers or oligomers that, when irradiated at said wavelength, undergo a photo-polymerization and/or photo-cross-linking reaction, or constituted by a polymer that at a UV wavelength undergoes a photo-degradation reaction, and a second electrically active or activatable structural portion which is substantially transparent to such predetermined UV wavelength; exposing a portion of the active material, through a photomask, to UV radiation having such UV wavelength, with photo-activation of the exposed portion of such film; selectively removing either the exposed photo-activated portion or the non-exposed portion, with exposure of a respective portion of the bottom electrode; depositing a head electrode.

Abstract: A method for forming a memory cell including a selection transistor and an antifuse transistor, in a technological process adapted to the manufacturing of a first and of a second types of MOS transistors of different gate thicknesses, this method including the steps of: forming the selection transistor according to the steps of manufacturing of the N-channel transistor of the second type; and forming the antifuse transistor essentially according the steps of manufacturing of the N-channel transistor of the first type, by modifying the following step: instead of performing a P-type implantation in the channel region at the same time as in the N-channel transistors of the first type, performing an N-type implantation in the channel region at the same time as in the P-channel transistors of the first type.

Abstract: An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene.

Abstract: A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel.

Abstract: Methods and systems are disclosed for reduced power consumption in communication networks, including sensor networks implemented according to IEEE 802.11ah, by organizing stations into groups having long sleep periods. By organizing the stations of the network into groups, the access point can match each group's traffic identification map with its target beacon transmit time. One embodiment organizes the stations sequentially by AID numbers. Other embodiments organize the stations by similar power save requirements and/or nearby geographical location. Forms of an Extended Traffic Identification Map are matched with an awaken Target Beacon Transmit Time of the group.

Abstract: An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced.

Abstract: An embodiment described herein includes a method for producing a wafer of a first semiconductor material. Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer of the first material on the first layer.

Abstract: A digital imaging sensor includes an array of pixels. A subset of the pixels in the array has reduced photosensitivity in comparison to other pixels in said array. A controller operates to control an integration time of the array of pixels such that a first integration time of the subset of pixels is longer than a second integration time of the other pixels in the array. Such an image sensor is particularly useful for sensing light sources that are not illuminated continuously.

Abstract: An authentication method of a first module by a second module includes the steps of generating a first random datum by the second module to be sent to the first module, generating a first number by the first module starting from the first datum and by way of a private key, and generating a second number by the second module to be compared with the first number, so as to authenticate the first module. The step of generating the second number is performed starting from public parameters and is independent of the step of generating the first number.

Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.

Abstract: An image sensor including a pixel array, each pixel including, in a substrate of a doped semiconductor material of a first conductivity type, a first doped region of a second conductivity type at the surface of the substrate; an insulating trench surrounding the first region; a second doped region of the first conductivity type, more heavily doped than the substrate, at the surface of the substrate and surrounding the trench; a third doped region of the second conductivity type, forming with the substrate a photodiode junction, extending in depth into the substrate under the first and second regions and being connected to the first region; and a fourth region, more lightly doped than the second and third regions, interposed between the second and third regions and in contact with the first region and/or with the third region.

Abstract: An optical navigation device, including a radiation source capable of producing a beam of radiation; a sensor for receiving an image; and an optical element for identifying movement of an object on a first surface to thereby enable a control action to be carried out. The optical element is such that a whole of the imaged area of the first surface is substantially covered by the object in normal use. The device is operable to receive from the object on the first surface an input describing a pattern, to compare the received pattern to a stored reference pattern and to perform a predetermined function if the received pattern and stored reference pattern are substantially similar. The pattern may be a continuous line, the device being operable to store the continuous line as a set of turning points in chronological order.

Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract: The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories.

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract: In an electrostatic micromotor, a mobile substrate faces a fixed substrate and is suspended over the fixed substrate at a given distance of separation in an operative resting condition; an actuation unit is configured so as to give rise to a relative movement of the mobile substrate with respect to the fixed substrate in a direction of movement during an operative condition of actuation. The actuation unit is also configured so as to bring the mobile substrate and the fixed substrate substantially into contact and to keep them in contact during the operative condition of actuation. The electrostatic micromotor is provided with an electronic unit for reducing friction, configured so as to reduce a friction generated by the contact between the rotor substrate and the stator substrate during the relative movement.

Abstract: A method of forming dummy structures in accordance with the golden ratio to reduce dishing and erosion during a chemical mechanical polish. The method includes determining at least one unfilled portion of a die prior to a chemical mechanical planarization and filling the at least one unfilled portion with a plurality of dummy structures, a ratio of the dummy structures to a total area of the unfilled portion being in the range of 36 percent and 39 percent. A die formed in accordance with the method may include a plurality of metal levels and a plurality of regions at each metal level, each region having a plurality of dummy structures formed as golden rectangles.

Abstract: Front-side integrated parts of integrated-circuit chips are produced at locations on a substrate wafer. The front-side parts have a front side. A support wafer having a bearing side is mounted with the bearing side on top of said front-side parts. The support wafer includes at least one weak surface layer. This weak surface layer is attached to the substrate wafer using a retaining adhesive. In one implementation, the weak surface layer is attached to a front surface of the wafer. In another implementation, the weak surface layer is attached to a peripheral edge of the wafer. After attaching the support wafer, back-side integrated parts of the integrated-circuit chips are produced on the substrate wafer. The weak surface layer is then destroyed so as to demount the support wafer from the substrate wafer.

Abstract: A power device is formed by a thyristor and by a MOSFET transistor, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and a third current-conduction terminal connected to the thyristor for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reverse-bias safe-operating area.