Abstract: A control device for a power factor correction device in forced switching power supplies is disclosed; the device for correcting the power factor comprises a converter and said control device is coupled with the converter to obtain from an input alternating line voltage a regulated output voltage. The converter comprises a power transistor and the control device comprises a driving circuit of said power transistor; the driving circuit comprises a timer suitable for setting the switch-off period of said power transistor. The timer is coupled with the alternating line voltage in input to the converter and is suitable for determining the switch-off period of the power transistor in function of the value of the alternating line voltage in input to the converter.

Abstract: A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.

Abstract: A system and method is disclosed for providing an adaptive value of a TTL (Time to Live) count for broadcast/multicast messages in a wireless mesh network using a hybrid wireless mesh protocol. A mesh point controller is provided that adaptively selects the value of the TTL count and routes the broadcast/multicast message through the wireless mesh network based on the adaptively selected value of the TTL count. The adaptive selection of the TTL count in accordance with the principles of the invention significantly reduces the number of broadcast/multicast messages that must be transmitted (flooded) through the mesh network.

Abstract: A structure including at least two neighboring components, capable of operating at high frequencies, formed in a thin silicon substrate extending on a silicon support and separated therefrom by an insulating layer, the components being laterally separated by insulating regions. The silicon support has, at least in the vicinity of its portion in contact with the insulating layer, a resistivity greater than or equal to 1,000 ohms.cm.

Abstract: A system for decoding a stream of compressed digital video images comprises a graphics accelerator for reading the stream of compressed digital video images, creating, starting from said stream of compressed digital video images, three-dimensional scenes to be rendered, and converting the three-dimensional scenes to be rendered into decoded video images. The graphics accelerator is preferentially configured as pipeline selectively switchable between operation in a graphics context and operation for decoding the stream of video images. The graphics accelerator is controllable during operation for decoding the stream of compressed digital video images via a set of application programming interfaces comprising, in addition to new APIs, also standard APIs for operation of the graphics accelerator in a graphics context.

Abstract: A system and method is disclosed for implementing a multipoint control unit in an endpoint that is participating in and managing a multipoint audio conference in a packet network. The multipoint control unit establishes audio communications between a plurality of endpoints of the packet network, mixes audio communications from the plurality of endpoints, and provides echo cancellation for the endpoint that is managing the multipoint audio conference.

Abstract: A system for implementing a cyclic digital to analog converter (c-DAC) is capable of supporting a large size liquid crystal display. The system includes an upper DAC stage configured to output a first voltage between a lower voltage supply (HVDD) and an upper voltage supply (AVDD). The system also includes a lower DAC stage configured to output a second voltage between the lower voltage supply (HVDD) and a ground. The upper DAC stage includes a single PMOS switch and the lower DAC stage includes a single NMOS switch.

Abstract: An embodiment of a voltage converter, provided with: a voltage transformer having a primary winding receiving an input voltage, a secondary winding supplying an output voltage, and an auxiliary winding supplying a feedback voltage correlated to the output voltage; a main switch, coupled to the primary winding; a control circuit, which controls switching of the main switch and has a sampling stage for sampling and holding the feedback voltage and supplying a sampled signal; and a voltage limiting circuit, provided with a clamp capacitor, designed to be coupled across the primary winding. A sampling control stage is coupled to the sampling stage, and is designed, during a given operating condition of the voltage converter, to enable updating of the sampled signal on the basis of a state of charge of the clamp capacitor.

Abstract: The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: A self-coexistence window reservation protocol for a plurality of Wireless Regional Area Network (WRAN) cells operating in a WRAN over a plurality of channels includes a sequence of self-coexistence windows that uniquely identifies a transmission period for each WRAN cell. A self-coexistence window reservation protocol is included within the first packet of a Coexistence Beaconing Protocol period identifying when each WRAN cell associated with a particular channel will transmit. When not actively transmitting, a WRAN cells remains in a passive, receiving mode to accept data. As the transmissions of each WRAN cell operating on a particular channel are scheduled, contention for a transmission period is eliminated.

Abstract: A thermoelectric generator including a sheet of a deformable material containing closed cavities, each of which contains a drop of a vaporizable liquid, and a mechanism for transforming into electricity the power resulting from the deformation of the sheet linked to the evaporation/condensation of the liquid.

Abstract: An analog-to-digital converter has a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components. The converter includes a first generator configured to generate a first analog value, a digital-to-analog converter configured to generate a second analog value, a second generator configured to generate a digital value from the comparison of the first analog value with respect to the second analog value, a controller configured to receive a signal indicating a test mode and to generate a configuration signal to the first generator, to receive the digital value and generate a control signal to control the generation of the second analog value, and to generate from the digital value an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

Abstract: A process for determining the displacement of an entity equipped with a sensor for capturing a sequence of images, comprising a step for determining a motion vector associated with a current image as a function of at least one correlation calculation between a first block of pixels in the current image and a second block of pixels from which the vector points towards said first block of pixels, with said second block being in a previous image in the sequence of images, wherein the dimensions of the first block are determined as a function of at least a motion vector associated with a previous image in the image sequence.

Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: A system is capable of assisting in reset of a data storage array including data storage array including one or more data storage array nodes. The system includes a control unit coupled to the data storage array configured to produce a control signal to reset the data storage array, and a reset unit communicatively coupled to the data storage array and the control unit configured to reset the data storage array by charge injection to the one or more data storage array nodes.

Abstract: A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data. The data processor generates the enhanced virtual image by generating a first component virtual image at a first depth plane, generating a second component virtual image at a second depth plane, and inserting first selected pixels from the first component virtual image into enhanced the virtual image and inserting second selected pixels from the second component virtual image into the enhanced virtual image.