Abstract: A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

Abstract: A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal.

Abstract: A video decoder receiving an encoded bit stream includes a header decoder which receives the encoded bit stream, a variable length decoder connected to the header decoder which receives the header decoded data, a quantizer and compensator connected to the variable length decoder, for, during backward decoding, performing inverse quantization, transformation and motion compensation of the variable length decoded data.

Abstract: For voltage interpolation amplifiers used in digital-to-analog converter architecture, the number of input differential pairs required by the voltage interpolation amplifier may be reduced such that an N-bit voltage interpolation amplifier comprises N+1 input differential pairs connected through a resistor attenuation network to provide a binary-weighted effective transconductance. In comparison to conventional voltage interpolation amplifier designs, the number of input differential pairs and power consumed by the circuit is significantly reduced, thereby creating a more area- and power-efficient voltage interpolation amplifier.

Abstract: A cache memory system comprises a cache memory and a cache controller that receives a first address to access the cache memory. The cache controller includes a first address transformer receives the first address and to transform it into one first cache address; the first cache address is used for accessing the cache memory to retrieve a first part of a tag address portion. The cache controller includes a hit detector establishes an partial hit condition based on a comparison of the retrieved a first part of the tag address portion and a first predetermined part of the first address, and a second address transformer receives the first address and to transform it into one second cache address. The cache controller uses the one second cache address for accessing the cache memory to retrieve a data word in case the partial hit condition is established.

Abstract: A plurality of resistive paths are coupled in parallel to a common node. A high side driver is operable responsive to first control signals to selectively supply current to certain ones of the resistive paths. A low side driver, including a plurality of selectively actuated current sink paths, is provided to sink current from the common node. A control logic circuit actuates a current sink path within the low side driver for each resistive path that is selectively supplied current by the high side driver. A substantially constant low side voltage drop through these sink paths is provided regardless of the number of resistive paths that are supplied current by the high side driver. A switched high side and low side configuration operating in an analogous way is also disclosed.

Abstract: A system and method provide adaptive frequency scaling for predicting the load on a processing unit and dynamically changing its clock frequency while keeping the synchronization with other processing units. The amount of data in an input memory waiting to be processed is a good indicator of the current load and thus embodiments utilize the same concept for predicting the load on the processing unit. The frequency of operation is thus changed on the basis of the percentage of memory being occupied by its input data. Algorithms according to embodiments allow the processing unit to use the maximum possible clock frequency only when it is required and to run at some lower frequencies in low processing power requirements. Operating the circuit at low frequency helps in reducing power consumption.

Abstract: A method for determining gain of a back-electromotive force amplifier may include setting an electric motor into a tri-state function mode and storing a first quasi steady-state value for back-electromotive force from the difference signal, and forcing a reference current through the electric motor and determining a first value of the gain of the amplifier for equaling a difference signal to the first quasi steady-state value. The method may further include setting the electric motor into a tri-state function mode a second time and storing a second quasi steady-state value for back-electromotive force from the difference signal, and increasing the first value of the gain by an amount proportional to a difference between the second quasi steady-state value and the first quasi steady-state value.

Abstract: A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors.

Abstract: A common control channel for base station (“BS”)/consumer premise equipment (“CPE”) communication in areas of overlapping coverage by wireless regional area network (“WRAN”) cells operating on different working channels is disclosed. A common control channel is selected from among the various working channels sensed in each of a plurality of overlapping WRAN cells so as to enable BS/CPE and BS/BS communication. Once chosen, each CPE within the overlapping area communicates with the controlling BS via an enhanced coexistence beacon protocol messages. These messages include timing and other synchronization information.

Abstract: A bi-directional protection circuit employs a single comparator for detecting fault conditions. Diodes are coupled between a detection node and voltage dividers setting references for inverting and non-inverting comparator inputs, each diode forward biased during one of the positive and negative halves of the alternating current input signal cycle and coupling the detection node to a respective one of the inverting and non-inverting comparator inputs, and reverse biased during the other of the positive and negative halves and decoupling the detection node from the other of the inverting and non-inverting comparator inputs. Upon an overcurrent condition during the positive half, a voltage at the inverting comparator input is drawn above the reference voltage at the non-inverting input. Upon an overcurrent condition during the negative half, a voltage at the non-inverting comparator input is drawn below the reference voltage at the inverting input.

Abstract: An embodiment of a power-supply controller comprises a switching-control circuit, an error amplifier, and a signal generator. The switching-control circuit is operable to control a switch coupled to a primary winding of a transformer, and the error amplifier has a first input node operable to receive a feedback signal, a second input node operable to receive a comparison signal, and an output node operable to provide a control signal to the switching-control circuit. The signal generator is operable to generate either the feedback signal or the comparison signal in response to a compensation signal that is isolated from a secondary winding of the transformer and that is proportional to a load current through a conductor disposed between the secondary winding and a load.

Abstract: A method of channel estimation in orthogonal frequency-division multiplexing communication employing three or more subcarriers, wherein frequency correlation exists between the subcarriers. The method includes: calculating a coarse channel estimate for each of the subcarriers, and calculating from the coarse channel estimates refined channel estimates for each of the subcarriers, wherein calculation of the refined channel estimates includes calculating the parameters of a Wiener Filter having a length of 2 L+1, where L is a positive integer, and filtering the coarse channel estimates with the Wiener Filter.

Abstract: A photodetector includes a photodiode and output circuitry coupled to the photodiode. The photodetector is configurable for operation in at least two modes. A first configurable mode operates the photodetector as an integrating sensor. In this first mode, a bias voltage across the photodiode is set below the breakdown voltage of the photodiode and the output circuitry is configured to read an analog integration output voltage from the photodiode. A second configurable mode operates the photodetector as a single photon avalanche detector. In this second mode, the bias voltage across the photodiode is set above the breakdown voltage of the photodiode and the output circuitry is configured to read an avalanche output voltage.

Abstract: An image sensor includes a pixel array and an image sensor objective optical element. The element is formed by a lenslet array. Each lenslet in the array directs incoming radiation onto a different specific pixel or sub-array of pixels in the pixel array. The lenslets in the array are shaped such that fields of view of next-but-one neighboring ones of the lenslets (i.e., two lenslets spaced from each other by another lenslet) do not overlap until a certain object distance away from the lenslet array.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to receive the transaction request including at least first source identity information, wherein the first source identity information is associated with a source of the transaction request on the further die. The mapping circuitry is configured to modify the transaction request to replace the first source identity information with local source identity information, wherein that local source identity information is associated with the mapping circuitry. The mapping circuitry is configured to modify the received transaction request to provide said first source identity information in a further field.

Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.

Abstract: A method and a circuit for detecting a binary state supported by an analog symbol, comprising sampling the symbol with a sampling signal based on a frequency having a period shorter than the duration of a symbol, selecting a number of significant samples smaller than the number of samples which would be obtained with a sampling of the symbol at said frequency, and deciding of the symbol state based on the selected samples.

Abstract: A low-dropout linear regulator includes an error amplifier comprising a cascaded arrangement of a differential amplifier and a gain stage having interposed therebetween a frequency compensation network for a loading current to flow therethrough. The regulator includes a current limiter inserted the flow-path of the loading current for the compensation network to increase the slew rate of the output of the differential amplifier by dispensing with the capacitive load in the frequency compensation network during load transients in the regulator.

Abstract: A method for cadence detection in a sequence of video fields is based on at least a search for cadence patterns in a sequence of bits representative of the motion in at least a part of the field from one field to another in the field sequence. The signaling of field skip and/or field repeat commands as applied to the fields in the field sequence is considered during the cadence detection operation so as to field skips and repeats.