Abstract: The device may include a contactless element and a set of least two auxiliary elements. Each auxiliary element may include a slave SWP interface connected to a same master SWP interface of the contactless element through a SWP link, and a management module configured for activating at once only one slave SWP interface on the SWP link.
Type:
Application
Filed:
October 26, 2011
Publication date:
May 3, 2012
Applicants:
STMicroelectronics GmbH, STMicroelectronics (Rousset) SAS
Inventors:
Laurent DEGAUQUE, Jürgen BÖHLER, Alexandre CHARLES, Pierre RIZZO
Abstract: A method of power recovery by an electromagnetic transponder in the field of a terminal, wherein: a ratio of the current coupling factor of the transponder with the terminal to an optimum coupling position with a resistive load value is evaluated; and a detuning of the oscillating circuit is caused if the ratio is greater than a first threshold greater than or equal to one.
Abstract: Systems and methods are disclosed that include reading passive engine status, detecting vibration, caused by the transfer of kinetic energy from at least one machine into the engine, and inhibiting active operation of the engine.
Abstract: A transmission line formed in a device including a stack of first and second chips having their front surfaces facing each other and wherein a layer of a filling material separates the front surface of the first chip from the front surface of the second chip, this line including: a conductive strip formed on the front surface side of the first chip in at least one metallization level of the first chip; and a ground plane made of a conductive material formed in at least one metallization level of the second chip.
Type:
Application
Filed:
October 21, 2011
Publication date:
May 3, 2012
Applicant:
STMicroelectronics S.A.
Inventors:
Pierre Bar, Sylvain Joblot, Jean-François Carpentier
Abstract: A method for carrying out nucleic acid amplification, includes providing a reaction chamber (31), accommodating an array (36) of nucleic acid probes (37) at respective locations, for hybridizing to respective target nucleic acids; and introducing a solution (50) into the reaction chamber (31), wherein the solution (50) contains primers, capable of binding to target nucleic acids, nucleotides, nucleic acid extending enzymes and a sample including nucleic acids. The a structure of the nucleic acid probes (37) and of the primers so that a hybridization temperature (TH) of the probes (37) is higher than an annealing temperature (TA) of the primers, whereby hybridization and annealing take place in respective separate temperature ranges (RH, RA).
Abstract: The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome.
Type:
Grant
Filed:
June 23, 2009
Date of Patent:
May 1, 2012
Assignee:
STMicroelectronics, Inc.
Inventors:
Anatoly Gelman, Russell Lawrence Schnapp
Abstract: A self-cooled electronic component comprising a vertical monolithic circuit, in which the vertical monolithic circuit is electrically connected in series with a Peltier cooler so that the D.C. current flowing through the circuit supplies the cooler and in which the circuit and the cooler are placed against each other so that the cold surface of the cooler is in thermal contact with the circuit.
Abstract: An active-set PAR reduction method has low computation cost and delay. Peak canceling, by adding up the original signal and the peak canceling signal, is done only after the final peak canceling signal that can reduce all peaks of the resultant signal below the desired peak level is generated with an iterative method or a maximum iteration is reached. The PAR reduction method cancels the high computation cost for accumulating the peak-canceling effort into each sample every iteration. In the i-th iteration, the method attempts to resolve an intermediate peak canceling signal that can reduce the i peaks of the resultant signal to the desired peak level. The method only calculates the samples of the intermediate peak canceling signal and performs balance testing in some locations where the peak level of the original signal is larger than a selected threshold.
Abstract: The dielectric of a capacitor is formed by superposition of at least two thin layers made from the same metal oxide, respectively in crystalline and amorphous form and respectively presenting quadratic voltage coefficients of capacitance of opposite signs.
Type:
Grant
Filed:
October 16, 2007
Date of Patent:
May 1, 2012
Assignees:
Commissariat a l'Energie Atomique, STMicroelectronics (Crolles 2) S.A.S.
Abstract: A graphic system having a central processing unit; a system memory coupled to the central processing unit; a display unit provided with a corresponding screen; a graphic module coupled to and controlled by the central processing unit to render an image on the screen of the display unit, the graphic module including a fragment graphic module having a depth test buffer for storing a current depth value; a depth test stage coupled to the depth test buffer for comparing the current depth value with a depth coordinate associated with an incoming fragment and defining a resulting fragment; a test stage for testing the resulting fragment and defining a retained fragment; a buffer writing stage operatively associated with the test stage for receiving the retained fragment, the buffer writing stage coupled to the depth test buffer for updating the current depth value with a depth value of the retained fragment.
Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.
Abstract: A method of detecting an angular position of a rotor of a motor includes detecting switching ripple peaks and armature current disturbance peaks using a peak detector configured to generate a square wave having edges coinciding with detected peaks. The method further includes filtering the square wave in a time domain by generating an integration ramp, toward a set value, of an estimated ripple frequency for an interval of time based on the estimated ripple frequency. An enablement range is established to reset the integration ramp by setting a threshold below and above the set value and a time window centered on an end time of each period of the estimated ripple frequency. The method further includes resetting the integration ramp, and updating the estimated ripple frequency based upon a period determined by a time of the resetting, if an edge of the square wave is within the time window.
Abstract: Described herein are techniques for forming, during wafer processing, a conductive shielding layer for a chip formed from a wafer. The conductive shielding layer can be formed on multiple sides of a chip prior to dicing the wafer to separate the chip from the wafer. A wafer may be processed to form trenches that extend substantially through the wafer. The trenches may be formed opposite scribe lines that identify boundaries between chips of the wafer and may extend through the wafer toward the scribe lines. A shielding layer may be formed along the trenches.
Abstract: An imaging device may be formed in a semiconductor substrate including a matrix array of photosites extending in a first direction and a second direction. The imaging device may include a transfer module configured to transfer charge in the first direction and an extraction module configured to extract charge in the second direction.
Abstract: A line-powered LED driver is operable to provide primary-side regulation of output current supplied to LED circuitry. The circuit includes a feedback loop coupled to a power converter, wherein the feedback loop adds scaled input current to scaled input voltage to produce a control signal. The power converter is responsive to the control signal to adjust input current drawn by the power converter in response to changes in line voltage to provide constant input power. The power converter produces output power for supplying constant output current at the LEDs. The feedback loop may use a reference voltage derived from the LED circuitry so that the output power may be regulated to provide constant LED current for varying LED voltages. When compared to secondary-side current feedback schemes, the LED driver provides increased efficiency and reliability at a reduced cost by implementing primary-side regulation of the output current.
Abstract: A method of transmission over a serial bus, between a master circuit and two slave circuits, wherein each slave circuit makes the transmission of a first one of two binary states depend on the absence of a transmission of the second binary state by the other slave circuit.
Abstract: An automatic frequency selection circuit includes a base filter for receiving a video input, a peaking filter for receiving the video input, a first energy computation unit coupled to an output of the base filter, a second energy computation unit coupled to an output of the peaking filter, an automatic frequency control unit to compare relative measured energies of the first and second energy computation units and to output a temporarily stable selected frequency for a targeted attenuation, and a frame delay feedback unit for receiving the temporarily stable selected frequency coupled to the peaking filter.
Type:
Application
Filed:
October 20, 2010
Publication date:
April 26, 2012
Applicant:
STMicroelectronics Asia Pacific Pte Ltd.
Abstract: A portable video player includes: a data input coupled to a memory module to store at least one video file, a video decoder coupled to the memory module via a memory interface to decode the video file, and a video interface connector to output to a display the decoded video file.
Abstract: A method of sensing an amplitude and a phase of a varying electrical signal representing an impedance of an electrically conductive tissue through which an AC stimulation current is forced may include measuring a first amplitude value of the varying electrical signal corresponding to an arbitrary initial phase offset value and assuming the first amplitude value corresponds to the amplitude and assuming the arbitrary initial phase offset value corresponds to the phase. The method may include measuring a second amplitude value of the varying electrical signal at a phase offset different from the phase. The method may further include comparing the second amplitude value with the amplitude, and updating the amplitude and the phase to correspond to one of a maximum and a minimum amplitude value and to a corresponding phase offset.
Abstract: Device for processing an analogue signal, comprising an analogue-digital converter with a pipelined architecture having an offset, and compensation means configured to compensate for the said offset, the said compensation means comprising digital correction means configured to correct the integer portion of the offset based on the digital signal delivered by the analogue-digital converter, and analogue correction means included in the last stage of the analogue-digital converter and configured to correct the decimal portion of the offset.
Type:
Application
Filed:
September 23, 2011
Publication date:
April 26, 2012
Applicants:
STMicroelectronics (Grenoble 2) SAS, STMicroelectronics SA
Inventors:
Roger Petigny, Hugo Gicquel, Sophie Minot