Abstract: This invention relates to cognitive radio based wireless communications of dynamic spectrum access networks, and more particularly to a method of addressing radio frequency sensing control and dynamic frequency selection control. A method called Cognitive Dynamic Frequency Hopping that is based on the selective Simultaneous Sensing and Data Transmissions is described. The Cognitive Dynamic Frequency Hopping method is further facilitated by a collision avoidance technique. The described method satisfies both reliable and timely RF sensing for guaranteeing licensed user protection, and QoS satisfaction for services of the dynamic spectrum access systems.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract: A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

Abstract: A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period.

Abstract: The invention relates to a method for selective deposition of Si or SiGe on a Si or SiGe surface. The method exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: An electrically programmable non-volatile memory device includes a plurality of memory cells, a plurality of lines for selectively biasing the memory cells, reconnection circuitry for reconnecting a pair of selected lines having different voltages, and a controller for controlling the memory device. The reconnection means includes a discharge circuit for discharging one of the selected lines being at the higher voltage in absolute value, an equalization circuit for equalizing the selected lines, a comparator circuit for measuring an indication of a voltage difference between the selected lines, and an evaluation circuit responsive to an enabling signal from the controller for activating the discharge circuit until an absolute value of the voltage difference exceeds a threshold value and for disabling the discharge circuit and enabling the equalization circuit when the absolute value of the voltage difference reaches the threshold value.

Abstract: An electrically programmable non-volatile memory device being integrated on a chip of semiconductor material is proposed.

Abstract: A passive integrated circuit formed on a substrate, including contact areas of a conductive material specifically capable of receiving bonding pads, wherein the conductive material further creates connections between regions of a lower metallization level.

Abstract: A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

Abstract: Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test operating mode making it possible to check the proper operation of the sequential electronic circuit (10). The clock signal (CK) used in the normal operating mode is used to gate the circuit (10) during the test operating mode.

Abstract: A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame.

Abstract: A method of generating at least one test sequence for testing a data connection, the method involving selectively combining by a logic function (206) the output sequences of a plurality of pseudo-random bit sequence (PRBS) generators (202, 204), each generator having a specific number of states that is different from those of the other generators.

Abstract: A method of controlling a synchronous motor that may include windings and a power driving stage coupled to the windings, may include using a feedback loop including using a feedback circuit coupled to the windings to generate current feedback components, using current controllers for generating respective voltage signals, and using an anti-transform circuit for generating control signals for the power driving stage. Using the feedback loop may include generating additional compensation signals for compensating the control signals, and adding the additional compensation signals from the current controllers by one of generating the additional compensation signals as quadrature and direct voltage compensation signals and adding them to the voltage signals to generate compensated quadrature and direct signals, and supplying the compensated quadrature and direct signals to the power driving stage by providing the compensated quadrature and direct signals to the anti-transform circuit.

Abstract: An apparatus is provided that comprises a test circuit; a first receiver unit arranged to receive test commands and to provide the test commands to the test circuit; a power supply unit arranged to supply power to the test circuit and to the first receiver unit; a second receiver unit arranged to receive power commands. The second receiver is arranged to control the operation of the power supply unit in response to the power commands received by the second receiver unit.

Abstract: A method for evaluating the current coupling factor between an electromagnetic transponder and a terminal, and a transponder implementing this method, wherein a ratio between data representative of a voltage across an oscillating circuit of the transponder and obtained for two capacitance values of the oscillating circuit is compared with one or several thresholds.

Abstract: A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second MOS transistor of lower leakage current, wherein the second cell takes up the same surface area as the first cell, and the second MOS transistor has a gate of same length as the gate of the first MOS transistor across at least a first width in its central portion, and of greater length across at least a second width on either side of the central portion.

Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.

Abstract: A structure for protecting a circuit connected to first and second rails of a telephone connection against overvoltages, including: first and second diodes in anti-series between the first and second rails; a first capacitor in parallel with a first resistor between a first node common to the first and second diodes and a low voltage reference node; and a protection element capable of removing fast overvoltages between any of the rails and the low reference voltage node when these overvoltages exceed a first threshold associated with the voltage of the first node.

Abstract: The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions (310, 312, 314) of a first search window (108); generating a cumulative score based on results of said one or more tests on said plurality of sub-regions; comparing said cumulative score with a threshold value; and based on said comparison, selectively performing one or more of said tests of said test sequence on at least one further sub-region of said first search window, said at least one further sub-region at least partially overlapping each of said plurality of sub-regions.

Abstract: A method for designing masks adapted to the forming of integrated circuits, including the steps of: (a) forming a first test file including a set of configurations of integrated circuit elements; (b) forming a second test file comprising the elements of the first test file, less the elements corresponding to configurations forbidden by design rule manuals; (c) trans-forming the second test file by means of a set of logical operations implemented by computing means to obtain a mask file; (d) testing the mask file and, if the test is negative, modifying the design rule manuals; and (e) repeating steps (a) to (d) until the test of step (d) is positive.