Abstract: A power amplifier formed by a plurality of pairs of transistors, each pair including a first transistor and a second transistor having each a respective input terminal and a respective output terminal. The output terminals of the first and second transistors of each pair are connected to an output distributed active transformer connected to a differential output of the power amplifier. The input terminals of the first and second transistors of each pair are connected to an input distributed active transformer connected to an input of the power amplifier.

Abstract: The method is for transmitting data between two devices via a clock wire or line and at least one data wire or line. The clock wire is maintained by default on a logic value A, and each device is capable of tying the clock wire to an electric potential representing a logic value B that is the opposite of A. According to the method, both devices tie the clock wire to B when a datum is transmitted, the device to which the datum is sent does not release the clock wire while it has not read the datum, and the device sending the datum maintains the datum on the data wire at least until an instant when the clock wire is released by the device to which the datum is sent. The method is particularly applicable to communication between a microcomputer and a microprocessor.

Abstract: A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a height smaller than the electrically conductive region. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.

Abstract: A method writes data in a non-volatile memory comprising memory cells that are erased before being written. The method comprises the steps of providing a main non-volatile memory area comprising target pages, providing an auxiliary non-volatile memory area comprising auxiliary pages, providing a look-up table to associate to an address of invalid target page an address of valid auxiliary page, and, in response to a command for writing a piece of data in a target page writing the piece of data as well as the address of the target page in a first erased auxiliary page, invalidating the target page, and updating the look-up table.

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract: A method writes data in a non-volatile memory. The method provides, in the memory, a non-volatile main memory area comprising target pages, a non-volatile auxiliary memory area comprising auxiliary pages, and, in the auxiliary memory area: a current sector comprising erased auxiliary pages usable to write data, a save sector comprising auxiliary pages comprising data linked to target pages to be erased or being erased, a transfer sector comprising auxiliary pages including data to be transferred to erased target pages, and an unavailable sector comprising auxiliary pages to be erased or being erased. The method can be applied in particular to FLASH memories.

Abstract: A device for correlating trend data with respect to a patient's weight ankle displacement can identify conditions indicative of congestive heart failure. A weight scale or similar device coupled with imaging mechanism operable to measure ankle displacement collects a plurality of measurements over a period of time. Over time trend analysis of both the patient's weight and the ankle displacement measurements can be obtained and compared to identify whether over a particular sample period an increase in a patient's ankle displacement is or is not correlated with an increase in the patient's weight. When an increase in ankle displacement is identified as not correlating to a corresponding change in the patient's weight an alert can be issued of conditions indicative of congestive heart failure.

Abstract: The method of processing a first digital image by combining the first digital image with a second digital image includes the first digital image being received from a pixel array, and when receiving the first digital image it is converted into a first continuous sequential data stream. The second digital image may be provided in the form of a second continuous sequential data stream, and the first and second digital images may be combined by continuously combining the data in the first and second data stream.

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

Abstract: An integrated network adapter is operable to establish a network interface with a plurality of media types, including at least a power line network and a telephone line network, based on pre-configuration, upon initialization and dynamically during operation. The adapter further is operable to establish network interfaces simultaneously or separately with a plurality of media types and provide that a communications event can occur simultaneously or separately over a plurality of media types.

Abstract: A memory element for a magnetic RAM, having a first magnetic portion in a first recess of a first insulating layer; and a non-magnetic portion and a second magnetic portion in a second recess of a second insulating layer covering the first insulating layer, the second recess exposing the first magnetic portion and a portion of the first insulating layer around the first magnetic portion, the non-magnetic portion being interposed between the first and second magnetic portions.

Abstract: Nanosized filamentary carbon structures (CNTs) nucleating over a catalyzed surface may be grown in an up-right direction reaching a second surface, spaced from the first surface, without the need of applying any external voltage source bias. The growth process may be inherently self-stopping, upon reaching a significant population of grown CNTs on the second surface. A gap between the two surfaces may be defined for CNT devices being simultaneously fabricated by common integrated circuit integration techniques. The process includes finding that for separation gaps of up to a hundred or more nanometers, a difference between the respective work functions of the materials delimiting the gap space, for example, different metallic materials or a doped semiconductor of different dopant concentration or type, may produce an electric field intensity orienting the growth of nucleated CNTs from the surface of one of the materials toward the surface of the other material.

Abstract: Authentication system comprising an input device comprising a plurality of input elements configured for inputting respectively characters in response to an input of a sequence of at least one character carried out by a user, the input device comprising at least one determination means coupled to at least one input element in order to determine a force exerted on the said at least one input element, the system comprising a recording means for recording a series of at least one force exerted on the said at least one input element, a memory configured for storing a series of at least one reference force, and comparison means configured for comparing the series of at least one exerted force with the series of at least one reference force.

Abstract: A sample and hold circuit includes a plurality of capacitors, a network of switches and a control circuit. The control circuit is operable to control the network of switches so as to sample an incoming signal onto at least some of the plurality of capacitors. In such an operation, each capacitor takes a sample of the incoming signal at a different time. The sample and hold circuit outputs a signal corresponding to an average of the samples.

Abstract: A chip configuration for dual board voltage compatibility comprising ballast I/O pads, regulator control block and VDDCO pad. If 1.8V is available on board, all 1.8V pads are connected to the package pins and the VDDCO pad is double bonded with one 1.8V package pin. This ensures that the regulator is in operation providing 1.2V supply to the core. If 1.2V is available on board, all 1.2V pads are bonded to the package pins and VDDCO pad is left unbonded. A weak pulldown ensures that the regulator is inoperational and the gate voltage of ballast transistor is pulled up. Now 1.2V pads directly get supply from the board through package pins and is provided to the core without suffering IR drop.

Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.

Abstract: An electronic device includes a semiconductor substrate of a first conductivity type and a drain layer adjacent the semiconductor substrate and having a plurality of drains. The drain layer includes a first semiconductor layer of the first conductivity type adjacent the semiconductor substrate, and at least one second semiconductor layer of a second conductivity type adjacent the first semiconductor layer. Moreover, a plurality of first column regions of the first conductivity type extends through the at least one second semiconductor layer to contact the first semiconductor layer. A plurality of second column regions of the second conductivity type delimits the plurality of first column regions. Furthermore, a plurality of body regions of the second conductivity type are adjacent respective ones of the plurality of second column regions.

Abstract: An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.

Abstract: A method of preventing concurrent or quasi-concurrent commutations of a pair of phase shift modulation (PSM) drive signals of an output bridge stage driving an electrical load includes establishing a threshold level of a programmed current level to be transmitted though the electrical load. The method also includes, if the programmed current level is lower than the threshold level, enhancing a time offset between commutation edges of the pair of PSM drive signals by a minimum time.