Abstract: A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol.

Abstract: A microelectromechanical gyroscope that includes a first mass oscillatable according to a first axis; an inertial sensor, including a second mass, drawn along by the first mass and constrained so as to oscillate according to a second axis, in response to a rotation of the gyroscope; a driving device coupled to the first mass so as to form a feedback control loop and configured to maintain the first mass in oscillation at a resonance frequency; and an open-loop reading device coupled to the inertial sensor for detecting displacements of the second mass according to the second axis. The driving device includes a read signal generator for supplying to the inertial sensor at least one read signal having the form of a square-wave signal of amplitude that sinusoidally varies with the resonance frequency.

Abstract: A moving-image signal, such as typically a luminance signal organized in blocks of pixels is coded via a technique that envisages the steps of: comparing a block to be coded with a plurality of candidate prediction blocks; determining, for each candidate prediction block, a respective value of an index representing the difference between the block to be coded and each candidate prediction block; and choosing between the candidate prediction blocks, as a function of the respective value of the aforesaid index, a prediction block to be used for coding of the block to be coded. The signal is sampled pixel by pixel on the block to be coded and on the plurality of candidate prediction blocks, thus generating respective surfaces representing the pattern of the signal in the block to be coded and in the candidate prediction blocks. Chosen as an index is an index of the parallelism between the aforesaid respective surfaces.

Abstract: In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum. The selected conductive material preferably has a hardness which is at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

Abstract: A logic level converter includes two first electronic switches coupled in a bi-stable flip-flop arrangement having at least one output line, and a forcing circuitry including two second electronic switches to force switching of the first electronic switches in the flip-flop arrangement. The forcing circuitry has an input terminal to receive a logic input signal having a given level to produce switching of the flip-flop arrangement and generate at the output line(s) of the flip-flop arrangement, a logic output signal(s) whose voltage level is converted with respect to the level of the logic input signal. The converter includes, interposed between each of the two first electronic switches in the flip-flop arrangement and a respective one of the second electronic switches in the forcing circuitry, at least one respective cascode electronic switch to limit the voltage across the two first electronic switches in the flip-flop arrangement.

Abstract: An image sensor has a pixel array and an input circuit. The input circuit includes a first input, a second input and two coupling capacitors. The first input receives an analog signal from a pixel of the pixel array which has a first level during a first calibration period and a second level during a second read period. The second input receives a reference ramp signal. A comparator circuit compares the ramp signal and the analog signal. The analog signal and the ramp signal are constantly read onto the coupling capacitors during both the first calibration period and the second read period. The ramp circuit begins providing the ramp signal during the second read period so as to determine the change in magnitude of the analog signal between the first calibration period and the second read period, the ramp circuit also begins providing the ramp signal during the first calibration period so as to compensate for any delay in the ramp circuit providing the ramp signal during the second read period.

Abstract: A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit.

Abstract: The metrics matrix may include at least one particular layer including at least one particular column having several metrics cues, respectively, situated in different rows. For the particular layer, the updating of the channel cue is associated with the particular column involving at each iteration one updated metric cue selected from all the metrics cues of the particular column. The row of the selected metric cues may change at each iteration.

Abstract: A circuit includes a switch, having first and second transistors, and a driving device for driving the switch. A latch circuit, coupled between respective common gate and source terminals of the first and second transistors, supplies the common gate terminal with first and second control signals to turn off and on the first and second transistors. The latch circuit comprises a flip-flop coupled to the common source terminal and having a reset terminal coupled to the common source terminal by a reset resistance, a set terminal coupled to the common source terminal by a set resistance and an output terminal coupled to the common gate terminal. The latch circuit further includes an activation circuit connected to the set and reset terminals of the flip-flop and to the common source terminal to dynamically short-circuit the set and reset resistances during the falling edges of the signal applied to the switch.

Abstract: The method is for managing the operation of a wireless communication device including several different communication modules respectively adapted to operate according to several given communication protocols including a UWB module operating according to a UWB protocol based on an OFDM modulation scheme. The method includes controlling the UWB module for scanning a chosen frequency band, and managing a communication to be performed by the device on the basis of the scanning result.

Abstract: A method and a circuit for reading an electronic charge retention element for a temporal measurement, of the type including at least one capacitive element whose dielectric exhibits a leakage and a transistor with insulated control terminal for reading the residual charges, the reading circuit including; two parallel branches between two supply terminals, each branch including at least one transistor of a first type and one transistor of a second type, the transistor of the second type of one of the branches consisting of that of the element to be read and the transistor of the second type of the other branch receiving, on its control terminal, a staircase signal, the respective drains of the transistors of the first type being connected to the respective inputs of a comparator whose output provides an indication of the residual voltage in the charge retention element.

Abstract: A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock.

Abstract: A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects.

Abstract: A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function.

Abstract: A phase interpolator receiving a first signal having an oscillation frequency Fin and providing a second signal having said oscillation frequency and having a phase shift ?? with respect to the first signal which depends on a third signal. The interpolator includes a variable phase-shifter receiving the first signal and providing the second signal, the phase-shifter circuit includes an oscillator having a variable natural frequency Fo controlled by a fourth signal; a phase comparator capable of receiving the first and second signals and of providing a fifth signal representative of said phase shift; and a unit capable of providing the fourth signal which depends on the third and fifth signals.

Abstract: A digital filtering algorithm preprocesses couplet defects prior to their being operated on by a main filtering algorithm that focuses on singlet defects. The preprocessing involves the replacement of one of the defective pixel values in the couplet with a pixel value that is known to be non-defective. In preferred embodiments, the selection of the pixel value in the couplet to be replaced is customized depending on the direction of scanning of the pixel array, and can take into account edge effects of border pixels.

Abstract: The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required noise transfer function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band signal-to-noise ratio (SNR) at the cost of higher out-of-band noise.

Abstract: A method for stacking and interconnecting integrated circuits includes providing at least two substrates; forming a trench in each substrate; filling the trench with an insulating material; forming, in each substrate, at least one conductive area; thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate at least one electrically insulated region within the closed perimeter delineated by the trench; bonding the substrates together; making at least one hole through the bonded substrates so that the hole passes at least partially through the conductive areas and passes through the insulated region of each substrate; and filling the hole with an electrically conductive material so as to obtain a conductive column that traverses the isolated region of each substrate and is in lateral electrical contact with the conductive areas.

Abstract: The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.

Abstract: A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties.