Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: Contactless differential coupling structures can be used to communicate signals between circuits located on separate chips or from one chip to a probing device. The contactless coupling structures avoid problems (breaks, erosion, corrosion) that can degrade the performance of ohmic-type contact pads. The contactless coupling structures comprise pairs of conductive pads placed in close proximity. Differential signals are applied across a first pair of differential pads, and the signals are coupled wirelessly to a mating pair of conductive pads. Circuitry for generating and receiving differential signals is described.

Abstract: A low voltage isolation switch is coupled between an input terminal suitable for receiving a high voltage signal and an output terminal suitable for transmitting this high voltage signal to a load. The isolation switch includes a first driving transistor coupled between a first reference terminal and an intermediate node, a second driving transistor coupled between the intermediate node and the second reference terminal, a control transistor connected across a diode block coupled between the input and output terminals. The control transistor has a control terminal connected to the intermediate node through a low voltage decoupling block that includes first and second substrate terminals, first and second parasitic capacitive element connected to these first and second substrate terminals, and first and second decoupling transistors coupled in parallel to each other and having control terminals connected to the first and second parasitic capacitive elements, respectively.

Abstract: A back-side illuminated image sensor formed from a thinned semiconductor substrate, wherein: a transparent conductive electrode, insulated from the substrate by an insulating layer, extends over the entire rear surface of the substrate; and conductive regions, insulated from the substrate by an insulating coating, extend perpendicularly from the front surface of the substrate to the electrode.

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals that includes an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. The semiconductor integrated circuit is provided with some functionality restricted in some way by preventing one or more hardware circuit elements from operating, such as an MPEG decoder, display engine, IO ports or main CPU. To enable the functionality, a subscriber must pay for a service and then receives an encrypted message broadcast to the semiconductor integrated circuit that is decrypted and instructs functionality to be turned on or off.

Abstract: A routing system is improved by performing three steps sequentially to complete an execution process. The first step estimates a normalized criticality score for each design net. The second step arranges the scores for each design net in descending order. Third step rips up and reroutes the design so as to make it more feasible.

Abstract: A magnetoresistive element formed by a strip of magnetoresistive material which extends on a substrate of semiconductor material having an upper surface. The strip comprises at least one planar portion which extends parallel to the upper surface, and at least one transverse portion which extends in a direction transverse to the upper surface. The transverse portion is formed on a transverse wall of a dig. By providing a number of magnetoresistive elements perpendicular to one another it is possible to obtain an electronic compass that is insensitive to oscillations with respect to the horizontal plane parallel to the surface of the Earth.

Abstract: In one embodiment, a method is provided for performing motion compensated interpolation wherein, for any pixels in the interpolated frame to which there is neither a forward vector nor a backward vector projecting: including the pixel in an intermediate frame conceal area if it is not located within the full frame reveal area; including the pixel in an intermediate frame reveal area if it is not located within the full frame conceal area; and using the intermediate frame conceal and reveal areas to interpolate values for pixels within an area of the interpolated frame.

Abstract: Methods and systems are described for displaying video data after a hot plug event during a start-up dead period. In particular, approaches for receiving data, determining whether link training can be performed and, if not, self-configuring a receiver to display the information in a proper format even during the dead period.

Abstract: The present disclosure is directed to a MEMS resonant structure, provided with a substrate of semiconductor material; a mobile mass suspended above the substrate and anchored to the substrate by constraint elements to be free to oscillate at a resonance frequency; and a fixed-electrode structure capacitively coupled to the mobile mass to form a capacitor with a capacitance that varies as a function of the oscillation of the mobile mass; the fixed-electrode structure arranged on a top surface of the substrate, and the constraint elements being configured in such a way that the mobile mass oscillates, in use, in a vertical direction, transverse to the top surface of the substrate, keeping substantially parallel to the top surface.

Abstract: A comparison circuit can reduce the amount of power consumed when searching a load queue or a store queue of a microprocessor. Some embodiments of the comparison circuit use a comparison unit that performs an initial comparison of addresses using a subset of the address bits. If the initial comparison results in a match, a second comparison unit can be enabled to compare another subset of the address bits.

Abstract: An analog switch configuration includes a gate control circuit coupled between an input of a switch and a gate of the switch. The gate control circuit passes voltage changes on the input of the switch to the gate of the switch to decrease the influence the inherent gate to input capacitance has on the bandwidth of the switch. By reducing the change in voltage across the inherent capacitance, the current through the capacitance in decreased as well as its influence on the bandwidth of the configuration.

Abstract: A method is provided. The method comprises calibrating noise prediction parameters by adapting one or more biases, adapting one or more filter coefficients using the adapted one or more biases, and adapting one or more prediction error variances using the adapted one or more biases and the adapted one or more filter coefficients.

Abstract: A process manufactures an interaction structure for a storage medium. The process includes forming a first interaction head provided with a first conductive region having a sub-lithographic dimension. The step of forming a first interaction head includes: forming on a surface a first delimitation region having a side wall; depositing a conductive portion having a deposition thickness substantially matching the sub-lithographic dimension on the side wall; and then defining the conductive portion. The sub-lithographic dimension preferably is between 1 and 50 nm, more preferably 20 nm.

Abstract: A generator of a voltage logarithmically variable with temperature may include a differential amplifier having a pair of transistors, each coupled with a respective bias network adapted to bias in a conduction state the transistors first and second respectively with a constant current and with a current proportional to the working absolute temperature. The pair of transistors may generate between their control nodes the voltage logarithmically variable with temperature. The differential amplifier may have a common bias current generator coupled between the common terminal of the differential pair of transistors and a node at a reference potential, and a feedback line to provide a path for the current difference between the sum of currents flowing through the transistors of the differential pair and the common bias current.

Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.

Abstract: A cyclic digital-to-analog converter includes a first capacitor and a second capacitor. Switching circuitry is selectively configurable to connect the first and second capacitors is at least two modes of operation, wherein a first mode uses the first capacitor during conversion of a bit as a sampling capacitor and uses the second capacitor during conversion of that bit as a holding capacitor, and wherein a second mode uses the second capacitor during conversion of a bit as a sampling capacitor and uses the first capacitor during conversion of that bit as a holding capacitor. A controller swaps converter operation between the first and second modes based on the bit values of a digital word to be converted. If adjacent bits of the digital word to be converted have different logical values, the converter swaps from the first mode to the second mode (or from the second mode to the first mode). Otherwise, the converted remains in the current first or second mode.

Abstract: A MEMS microbalance that includes a substrate made of semiconductor material with a cavity, and a resonator, which is suspended above the cavity of the substrate and is formed by a mobile body, by at least one first arm connected between the substrate and the mobile body, which has a first thickness and which enables oscillations of the mobile body with respect to the substrate, by an actuation transducer connected to the mobile body for generating the oscillations at a resonance frequency, and by a detection transducer for detecting a variation of the resonance frequency, wherein the mobile body possesses at least one thin portion having a second thickness smaller than the first thickness of the first arm.