Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract: A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Abstract: A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit.

Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.

Abstract: An analog-to-digital converter has a self-test capability that provides not only an indication of failure or performance degradation but also identifies the failed or degraded component or components. The converter includes a first generator configured to generate a first analog value, a digital-to-analog converter configured to generate a second analog value, a second generator configured to generate a digital value from the comparison of the first analog value with respect to the second analog value, a controller configured to receive a signal indicating a test mode and to generate a configuration signal to the first generator, to receive the digital value and generate a control signal to control the generation of the second analog value, and to generate from the digital value an alarm signal indicating a failure within the analog-to-digital converter or indicating a degradation of the performance of the analog-to-digital converter.

Abstract: A compound camera system for generating an enhanced virtual image having a large depth-of-field. The compound camera system comprises a plurality of component cameras for generating image data of an object and a data processor for generating the enhanced virtual image from the image data. The data processor generates the enhanced virtual image by generating a first component virtual image at a first depth plane, generating a second component virtual image at a second depth plane, and inserting first selected pixels from the first component virtual image into enhanced the virtual image and inserting second selected pixels from the second component virtual image into the enhanced virtual image.

Abstract: The disclosure relates to an integrated circuit comprising a data buffer circuit comprising first and second transistors coupled to a contact pad and third and fourth transistors. A first bias voltage is applied on a conduction terminal of the third transistor and a second bias voltage is applied on a conduction terminal of the fourth transistor. A third bias voltage less than the second bias voltage is applied on a control terminal of the first transistor and a fourth bias voltage greater than the first bias voltage is applied on a control terminal of the second transistor. Application notably for the production of a so-called “High Speed” USB port.

Abstract: A process for determining the displacement of an entity equipped with a sensor for capturing a sequence of images, comprising a step for determining a motion vector associated with a current image as a function of at least one correlation calculation between a first block of pixels in the current image and a second block of pixels from which the vector points towards said first block of pixels, with said second block being in a previous image in the sequence of images, wherein the dimensions of the first block are determined as a function of at least a motion vector associated with a previous image in the image sequence.

Abstract: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

Abstract: A system is capable of assisting in reset of a data storage array including data storage array including one or more data storage array nodes. The system includes a control unit coupled to the data storage array configured to produce a control signal to reset the data storage array, and a reset unit communicatively coupled to the data storage array and the control unit configured to reset the data storage array by charge injection to the one or more data storage array nodes.

Abstract: The disclosure relates to a method for etching a target layer, comprising: depositing a hard mask layer onto a target layer and onto the hard mask layer, a first photosensitive layer, exposing the first photosensitive layer through a first mask to transfer first patterns into the photosensitive layer, transferring the first patterns into the hard mask layer, depositing onto the hard mask layer etched a second photosensitive layer, exposing the second photosensitive layer through a second mask to transfer second patterns into the second photosensitive layer, transferring the second patterns into the hard mask layer by etching this layer, and transferring the first and second patterns into the target layer through the hard mask, the second patterns forming lines, and the first patterns forming trenches cutting the lines in the hard mask.

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract: The present disclosure relates to a method for enabling a virtual processing unit to access a peripheral unit, the virtual processing unit being implemented by a physical processing unit connected to the peripheral unit, the method comprising a step of transmitting to the peripheral unit a request sent by the virtual processing unit to access a service provided by the peripheral unit, the access request comprising at least one parameter and an identifier of the virtual unit, the method comprising steps, executed by the peripheral unit after receiving an access request, of allocating a set of registers to the virtual unit identifier received, storing the parameter received in the register set allocated, and when the peripheral unit is available for processing a request, selecting one of the register sets, and triggering a process in the peripheral unit from the parameters stored in the selected register set.

Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.

Abstract: A module of a biofuel cell includes three module elements each having a porous membrane. At least two of the porous membranes are electrically conducting and form the cathode and the anode of the biofuel cell. The third membrane, which is preferably positioned between the two electrically conducting membranes need not be conducting, but defines two emergent cavities within the module. A porous through-channel extends through a silicon support of the module so as to connect one of the emergent cavities to at least one external wall of the silicon support.

Abstract: A capacitive semiconductor pressure sensor, comprising: a bulk region of semiconductor material; a buried cavity overlying a first part of the bulk region; and a membrane suspended above said buried cavity, wherein, said bulk region and said membrane are formed in a monolithic substrate, and in that said monolithic substrate carries structures for transducing the deflection of said membrane into electrical signals, wherein said bulk region and said membrane form electrodes of a capacitive sensing element, and said transducer structures comprise contact structures in electrical contact with said membrane and with said bulk region.

Abstract: A system for exchanging information in an on-chip communication network using optical flow information for communication between Intellectual Property cores. The information is exchanged between a plurality of initiators and targets in the Intellectual Property cores. The system includes a router for propagating optical flow information from the initiators to the targets. Each initiator includes an interface to convert the traffic generated by the initiator and transmit it in the form of an optical flow within the on-chip communication network, and each target includes an interface to convert information from the optical form into the electrical form. The system is organized as a parametric system and includes programming module to define a first set of high level parameters, a second set of initiator network interface parameters and a third set of target network interface parameters.

Abstract: A method includes receiving first encoded data associated with one or more first lanes and decoding the first encoded data to produce decoded data. The method also includes encoding the decoded data to produce second encoded data associated with one or more second lanes and transmitting the second encoded data. In some embodiments, the method may further include multiplexing a plurality of code group sequences (the second encoded data) into the one or more second lanes, and the number of first lanes may be greater than the number of second lanes. In other embodiments, the method may also include demultiplexing a plurality of code group sequences from the one or more first lanes into a plurality of the second lanes, and the number of first lanes may be less than the number of second lanes.

Abstract: A method of detection of the presence of a contactless communication element by a terminal emitting an electromagnetic field, in which an oscillating circuit of the terminal is excited at a frequency which is made variable between two values surrounding a nominal tuning frequency of the oscillating circuit; a signal representative of the load of the oscillating circuit being interpreted to detect that a reference voltage has not been exceeded, which indicates the presence of an element in the field. A presence-detection circuit and a corresponding terminal.

Abstract: A circuit may generate a clock signal with a variable period given by a ratio between an initial switching period and a number of phase circuits through which a current of a multi-phase PWM voltage converter flows. The circuit may include an adjustable current generator driven by a signal representing the number of phase circuits through which the current flows and configured to generate a current proportional to the number of phase circuits through which the current flows, and a tank capacitor charged by the adjustable current generator. The circuit may include a comparator of a voltage on the tank capacitor with a threshold value configured to generate a pulse of the clock signal when the threshold value is attained, and a discharge path of the tank capacitor, the discharge path being enabled during the pulses of the clock signal.