Abstract: A general purpose register including two input ports and two output ports, each port being addressed by an independent addressing circuit. The general purpose register includes a number of internal registers, and the provision of four independent addresses enables data to be written into two internal registers while data is being read out of two internal registers. The general purpose register also includes circuitry for transferring data from the input ports directly to the output ports without entering the data into the internal registers. Interchanging of bytes of data input words is also accomplished by the general purpose register. The internal registers, the four independent addressing circuits, the data transferring circuitry and additional undedicated circuitry are integrated into a single chip.

Abstract: A system and method of connecting power supplies in parallel that provides desired voltage regulation at the load and current sharing between the power supplies. The power supplies are connected in parallel at the load. Each power supply also has a sense line connected at the load. Each power supply includes means for measuring the current delivered to the load. Each supply also includes an electronically controlled variable resistive element in its respective sense line. The amount of current being supplied by each power supply to the load is measured. A controller determines if an unacceptable imbalanced current condition exists, i.e., it determines which power supply is supplying too much or too little current and the controller selectively changes the value of the appropriate variable resistive element in the sense line of that power supply in order to change the current being delivered to the load in a direction that corrects for the imbalanced condition.

Abstract: A tool for aligning the leads or pins of a connector while they are inserted in the holes of the electronic package to which the connector will be attached is described. Guide rails, which are attached to a fixed-block on one end and a removable slidable block at the other end, are placed between the leads to align them in one direction. A comb having protruding teeth is positioned so that the teeth are placed between the leads in a direction perpendicular to the guide rails. The guide rails and teeth align and constrain the leads in the same pattern as the holes of the package and a clamp holds the guide rails and teeth in place. After the leads have been started to be inserted in the holes of the electronic package the comb is removed. The slidable block is removed from one end of the guide rails, and the guide rails are pulled out of their position between the leads. The connector leads are then fully inserted into the holes.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: An apparatus for supplying wire to a wire bonding mechanism is presented. Lengths of wire are fed to a low mass wire-loop reservoir while the bonding process is taking place. Wire is then supplied, at a high speed, from the wire-loop reservoir for the next bonding operation. The amount of wire supplied is precisely measured by measuring the change in the amount of wire stored in the reservoir. The apparatus can supply both single lead wire and twin lead wire. When twin lead wire is supplied, the two wires of the twin lead are separated at predetermined points before being fed to the wire-loop reservoir.

Abstract: A coupling arm for coupling a driving mechanism to a mechanism to be driven is presented. The arm includes a length of suitable rigid material with flexure points selectively formed therein. The flexure points allow the coupling arm to transmit a linear motion in both a forward and reverse direction without introducing backlash, yet allow the arm to flex in order to reduce stress forces caused by misalignment. The flexure points are formed by removing a sufficient amount of the rigid material at selected regions along the length thereof such that the remaining thickness allows the arm to bend. The coupling arm is ideally suited for applications requiring repeatable precision linear movement, such as a precise XY positioning table.

Abstract: An apparatus for removing lap soldered circuit packages from the module to which they are soldered is presented. The module is placed over the apparatus with the circuit package on the underneath side. A nozzle of the apparatus is raised so as to be centered below the circuit package, and a heated gas is directed over the lap soldered leads for a predetermined time. When the solder melts, gravity causes the circuit package to fall away from the module. The falling package is caught and held by the nozzle. The nozzle is then lowered away from the module, and as it is lowered, push rods protrude upwardly through the nozzle to support the circuit package and lift it out of the nozzle, thereby positioning the nozzle for easy and safe handling.

Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.

Abstract: A scannable asynchronous/synchronous CMOS latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the "master" portion and the second latch element acts as the "slave" portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch.

Abstract: An improved solder wave apparatus and method that minimizes the undesirable phenomenon of solder splash is presented. A V-shaped trough is placed across the top of the inner container or box of an otherwise conventional solder wave machine. The V-shaped trough is positioned so that the bottom thereof is lower than the lowest side wall or walls of the inner container. A hole in the bottom at a first end of the trough allows molten solder to enter therein. A dam is placed along the length of the trough and divides the trough into the first and second sections. The dam includes a hole at the bottom to allow molten solder to pass from the first section into the second section. A slot or opening placed in the side wall of the inner container above a second end of the trough allows the molten solder to fall back into an outer container of the solder wave machine, from which location the solder is pumped back into the inner container in conventional fashion.

Abstract: A process for forming the openings (vias) in the glass layer of complementary metal oxide semiconductor (CMOS) integrated circuit chips is presented. The pattern of openings is applied to the glass layer using conventional resist/mask techniques. A plasma is used to remove the glass, and the silicon dioxide layer, if there is one, to expose a portion of the N+ and P+ circuit elements. Decreased conductivity of the crystalline lattice structure of the N+ material, caused by exposure to the plasma, appears as an added resistor between the N+ material and the metallization layer. The added resistance is reduced to acceptable levels before the metallization layer is applied by placing the chip in an inert gas atmosphere at an appropriate elevated temperature for an appropriate time.

Abstract: A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits.

Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.

Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Abstract: A method and apparatus for reducing the number of areas multiply exposed when a workpiece is scanned by an electron beam or other exposing radiation. The areas to be exposed are described as a plurality of rectangular shapes. The method of the invention sorts the data describing the rectangles. Rectangles which overlap or abut in one direction and are coextensive in another are merged such that a smaller number of rectangles is formed. This smaller number describes an area substantially equivalent to the original pattern. The smaller number of rectangles resulting from the merging method will have a minimum of disadvantageously overlapping or abutting rectangles.

Abstract: An apparatus for aligning the leads of an integrated circuit (IC) package with respect to the pads of the printed circuit board to which they will be bonded is presented. An alignment fixture, comprising a coarse alignment pedestal mounted on a fine alignment block, receives the IC package on the alignment fixture and aligns the leads with respect to a reference coordinate system of the alignment fixture. A vacuum chuck is lowered to contact the aligned package, and is then raised to lift the aligned package off the fine alignment block while holding it in the aligned position. An X-Y table positions the printed circuit board under the aligned package. The vacuum chuck lowers the aligned package until the leads contact the pads, and holds it while the leads are bonded to the pads.

Abstract: A self-aligning process for adding a barrier metal to the source and drain regions of metal oxide semiconductors is presented. An oxide sidewall spacer is first formed on the sides of upwardly protruding gate regions. A barrier metal is then added to the entire surface, followed by adding a layer of resist material. The resist material is added in layers with each layer spun until the top surface is nearly smooth. An anisotropical etch is done to remove the resist everywhere except over the source and drain regions, which regions are depressed due to the upwardly protruding gate region and a surrounding upwardly protruding insulating material. The exposed barrier metal is etched away and the remaining resist is stripped, leaving a layer of barrier metal only over the source and drain regions.

Abstract: A connector arrangement for making connections between printed circuit boards and connectors located on parallel side panels such as the side panels of a card cage of a computer central processing unit. The printed circuit boards are part of modules which include a retractable connector arrangement. The connectors are moved to a retracted position in which their width is less than the spacing between connectors on the side panels to facilitate their insertion between the side panels. Once in position, the modules are moved to an extended position and connections are made between the modules connectors and those on the side panels. The connectors provide low cost, high reliability, high density connections and facilitate close center-to-center spacings between adjacent modules.

Abstract: A CMOS output circuit for an integrated circuit chip used in high speed computers is designed so that it can drive transmission line interconnects to thereby increase the speed of the transfer of signals between chips. The CMOS circuit can drive either a nonterminated transmission line, a terminated transmission line or a random wire. The output circuit enables both low power consumption and high speed to be achieved.