Patents Assigned to Storage Technology Partners
  • Patent number: 4545045
    Abstract: An automatic load/unload apparatus is disclosed for handling of workpieces that must be removed from protective cartridges prior to use. In particular, the workpiece to be handled is an optical disk adapted for use in an optical disk information storage device. The load/unload apparatus includes a guide frame, a cartridge pull-in tray, a cartridge insert separator, reciprocating means for moving the pull-in tray and separator, and an elevator assembly. During a load operation, the cartridge is inserted into the information storage device wherein the load/unload apparatus is housed. The cartridge is received in the guide frame and opened, allowing the pull-in tray to be slideably removed. The disk is separated from the pull-in tray and raised by the elevator assembly to a desired position. An unload operation proceeds in a reverse sequence.
    Type: Grant
    Filed: May 31, 1983
    Date of Patent: October 1, 1985
    Assignee: Storage Technology Partners II
    Inventors: James R. Baer, Kenneth Manes, Harold Lunka
  • Patent number: 4545047
    Abstract: A centering mechanism for centering the disk recording medium over the spindle of a rotating disk storage system is presented. The invention consists of a centerpiece in the disk having three or more fingers pointing in the direction of insertion and curved away from the center of the disk. As the disk is inserted over a tapered spindle, one side or the other of the fingers will contact the spindle and center the disk as it moves toward the tapered spindle. The bottom edge of the center hole of the disk is rounded to form a stop for the fingers. The fingers bend as the disk is inserted, and this stop ensures that the fingers will not bend too far and break. When the disk is fully inserted, all the fingers around the circumference of the hole are contacting the tapered spindle hub and are also bent back against the stop surface on the disk to provide good centering.
    Type: Grant
    Filed: January 31, 1984
    Date of Patent: October 1, 1985
    Assignee: Storage Technology Partners II
    Inventor: David W. Rickert
  • Patent number: 4542495
    Abstract: A hermetically sealed cassette cartridge is disclosed, which encapsulates an optical disk suitable for use in an optical information recording and retrieval device. The cassette cartridge comprises a structural casing having a cavity for containing said recording medium and a spindle hub adapter for rotating the disk for data access. Data transfer is accomplished through a flexibly mounted transparent window, said window serving not only as a hermetical seal but also to alleviate the need for a thick dust defocusing layer on the said encapsulated recording medium.
    Type: Grant
    Filed: October 31, 1983
    Date of Patent: September 17, 1985
    Assignee: Storage Technology Partners II
    Inventors: William R. A. Ziegler, Richard B. MacAnally
  • Patent number: 4542426
    Abstract: A flexible hub for a disk is described. The disk includes a relatively large center hole into which a flexible planar member is mounted or clamped. The size of the flexible member is slightly larger than the hole, thereby requiring that the flexible member be slightly bowed or flexed in order for it to fit within the hole. The flexible member is preferably attached to the disk at three respective equi-angularly spaced locations around the periphery of the hole. In the center of the flexible member is a collar adapted to receive a protruding spindle neck from a spindle mechanism upon which the disk is mounted. The end of the spindle neck and the inside wall of the collar are tapered at the same angle. Insertion of the spindle neck into the collar thereby forces alignment or centering of the center of the collar with the longitudinal axis of the spindle neck.
    Type: Grant
    Filed: May 31, 1983
    Date of Patent: September 17, 1985
    Assignee: Storage Technology Partners II
    Inventors: Richard A. Wilkinson, Jr., William C. Hunt, David W. Rickert
  • Patent number: 4540903
    Abstract: A scannable asynchronous/synchronous CMOS latch circuit that includes a first, second, and third latch element, an asynchronous latch section, and a clock control section. When operated as a synchronous latch, the first latch element operates as the "master" portion and the second latch element acts as the "slave" portion of a master/slave latch. The clock control circuit enables the clock signals to control the synchronous operation of the master/slave latch. When operated as an asynchronous latch, the clock control circuit disables the clock. The output of the asynchronous latch section is connected to the input of the first latch element. An asynchronous signal appearing on one of the inputs of the asynchronous latch section passes through the first and second latch elements and is applied to another input of the asynchronous latch section, causing it to be latched, or held. Separate outputs are provided for the asynchronous latch and the synchronous latch.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: September 10, 1985
    Assignee: Storage Technology Partners
    Inventors: Laurence H. Cooke, Robert A. Feretich, Richard F. Boyle
  • Patent number: 4526313
    Abstract: An improved solder wave apparatus and method that minimizes the undesirable phenomenon of solder splash is presented. A V-shaped trough is placed across the top of the inner container or box of an otherwise conventional solder wave machine. The V-shaped trough is positioned so that the bottom thereof is lower than the lowest side wall or walls of the inner container. A hole in the bottom at a first end of the trough allows molten solder to enter therein. A dam is placed along the length of the trough and divides the trough into the first and second sections. The dam includes a hole at the bottom to allow molten solder to pass from the first section into the second section. A slot or opening placed in the side wall of the inner container above a second end of the trough allows the molten solder to fall back into an outer container of the solder wave machine, from which location the solder is pumped back into the inner container in conventional fashion.
    Type: Grant
    Filed: March 22, 1983
    Date of Patent: July 2, 1985
    Assignee: Storage Technology Partners
    Inventors: Paul Hug, Antonio Tavares
  • Patent number: 4516145
    Abstract: A process for forming the openings (vias) in the glass layer of complementary metal oxide semiconductor (CMOS) integrated circuit chips is presented. The pattern of openings is applied to the glass layer using conventional resist/mask techniques. A plasma is used to remove the glass, and the silicon dioxide layer, if there is one, to expose a portion of the N+ and P+ circuit elements. Decreased conductivity of the crystalline lattice structure of the N+ material, caused by exposure to the plasma, appears as an added resistor between the N+ material and the metallization layer. The added resistance is reduced to acceptable levels before the metallization layer is applied by placing the chip in an inert gas atmosphere at an appropriate elevated temperature for an appropriate time.
    Type: Grant
    Filed: August 31, 1983
    Date of Patent: May 7, 1985
    Assignee: Storage Technology Partners
    Inventors: Jenq S. Chang, Tung S. Chang
  • Patent number: 4504783
    Abstract: A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits.
    Type: Grant
    Filed: September 30, 1982
    Date of Patent: March 12, 1985
    Assignee: STORAGE Technology Partners
    Inventors: John Zasio, Dwight Elvey, Ronald Tanizawa
  • Patent number: 4502136
    Abstract: The centering and clamping device consisting: a disk elevator, a disk support, a disk centering assembly, a disk clamping assembly, and a disk rotating assembly. In operation the disk is raised out of the disk insert tray cartridge by the disk elevating means and raised upward to engage a taper on the spindle of the device spin motor, moving upward until the cooperation between the taper on the neck spindle and the tapering on the disk centering collar cause the disk to move laterally until precisely centered on the spindle. Thereafter, the continued upward movement on the disk on the elevator lifting assembly causes a magnet located on the disk support means to come into magnetic contact with a steel plate on the spindle platform, thereby securely clamping the disk to the spindle for rotation. Thereafter, the elevator moved downward and clamping the disk from disk support means, thereby allowing the free rotation of the spindle disk and disk support assembly relative to a stationary elevating means.
    Type: Grant
    Filed: April 4, 1983
    Date of Patent: February 26, 1985
    Assignee: Storage Technology Partners II
    Inventors: David W. Rickert, Richard A. Wilkinson, Jr., William C. Hunt
  • Patent number: 4502099
    Abstract: An improved cooling system for electronic components wherein an air supply housing with two openings cooperates with a manifold with one opening to allow air distribution from the air supply housing through the manifold to a card cage both while the manifold is closed for normal operation and while the manifold is extended to allow maintenance of the electronic components. When the manifold is closed for normal operation, the first opening in the air supply housing is blocked by the manifold and air flows into the manifold through the second opening. When the manifold is extended for maintenance, air flows into the manifold through the first opening and the second opening is blocked by a flapper which swings down over the second air supply housing opening.
    Type: Grant
    Filed: May 27, 1983
    Date of Patent: February 26, 1985
    Assignee: Storage Technology Partners II
    Inventors: Kenneth L. Manes, William D. Hart
  • Patent number: 4497465
    Abstract: Disclosed is a low cost flexural mechanism upon which tracking mirrors and the like used in optical systems may be mounted. The flexural mechanism is made from a single sheet of metal by placing a desired shape or pattern in the metal. The resulting shape is then formed into a base, mounting surface, and flex arms. The mechanism is stiff in directions other than rotation, has low noise, has low thermal sensitivity, and can be made in any practical size. The flexural mechanism can be designed to place the pivot axis at the center of gravity of the mass being rotated, even when the center of gravity is outside the flexural mechanism.
    Type: Grant
    Filed: March 31, 1983
    Date of Patent: February 5, 1985
    Assignee: Storage Technology Partners II
    Inventors: Lester M. Yeakley, Karen M. Fitzgerald
  • Patent number: 4498165
    Abstract: A magnetic or optical disk load/unload device for automatically centering and clamping a disk to the spindle of an information storage device. The apparatus is comprised of a toggle arm, a toggle arm rotating device, a support base, a support hub having a centering stem and a concentric annular steel ring disposed on its mating surface, a member for clamping the hub to the support base, a spindle having a centering hole on its mating surface and a concentric magnetic material ring on its mating surface, and a spindle rotating motor. In operation, the toggle arm is rotated from a first bent position causing the support base hub and disk located thereon to advance toward the spindle, the hub slidably retained on the base by a of clamping member activated by a cam assembly. Upon full extension of the toggle arm, the hub and disk are centered on the spindle, clamped to same by the magnetic and steel rings.
    Type: Grant
    Filed: October 3, 1983
    Date of Patent: February 5, 1985
    Assignee: Storage Technology Partners II
    Inventor: Richard A. Wilkinson, Jr.
  • Patent number: 4495629
    Abstract: An improved scannable latch circuit allows its output to be monitored during effectively 100% of the system clock cycle. The circuit further provides dual isolated outputs, one of which is used as a latch output and the other of which is used as a shift-register output. A computer system, in which the scannable latch circuit is used, in conjunction with combinatorial logic and error detection circuitry, may thus monitor the latch output, which is not loaded down by the shift register output, for error detection and other purposes without having to slow down the system operating speed. A preferred embodiment of the scannable latch circuit includes first, second, and third latch elements. When operating a latch circuit, the first latch element operates as the "master" and the second latch element operates as the "slave" of a master/slave latch circuit.
    Type: Grant
    Filed: January 25, 1983
    Date of Patent: January 22, 1985
    Assignee: Storage Technology Partners
    Inventors: John J. Zasio, Larry Cooke
  • Patent number: 4495628
    Abstract: A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.
    Type: Grant
    Filed: June 17, 1982
    Date of Patent: January 22, 1985
    Assignee: Storage Technology Partners
    Inventor: John J. Zasio
  • Patent number: 4482810
    Abstract: A method and apparatus for reducing the number of areas multiply exposed when a workpiece is scanned by an electron beam or other exposing radiation. The areas to be exposed are described as a plurality of rectangular shapes. The method of the invention sorts the data describing the rectangles. Rectangles which overlap or abut in one direction and are coextensive in another are merged such that a smaller number of rectangles is formed. This smaller number describes an area substantially equivalent to the original pattern. The smaller number of rectangles resulting from the merging method will have a minimum of disadvantageously overlapping or abutting rectangles.
    Type: Grant
    Filed: September 30, 1982
    Date of Patent: November 13, 1984
    Assignee: Storage Technology Partners
    Inventor: Larry Cooke
  • Patent number: 4479298
    Abstract: An apparatus for aligning the leads of an integrated circuit (IC) package with respect to the pads of the printed circuit board to which they will be bonded is presented. An alignment fixture, comprising a coarse alignment pedestal mounted on a fine alignment block, receives the IC package on the alignment fixture and aligns the leads with respect to a reference coordinate system of the alignment fixture. A vacuum chuck is lowered to contact the aligned package, and is then raised to lift the aligned package off the fine alignment block while holding it in the aligned position. An X-Y table positions the printed circuit board under the aligned package. The vacuum chuck lowers the aligned package until the leads contact the pads, and holds it while the leads are bonded to the pads.
    Type: Grant
    Filed: July 26, 1983
    Date of Patent: October 30, 1984
    Assignee: Storage Technology Partners
    Inventor: Paul Hug
  • Patent number: 4478679
    Abstract: A self-aligning process for adding a barrier metal to the source and drain regions of metal oxide semiconductors is presented. An oxide sidewall spacer is first formed on the sides of upwardly protruding gate regions. A barrier metal is then added to the entire surface, followed by adding a layer of resist material. The resist material is added in layers with each layer spun until the top surface is nearly smooth. An anisotropical etch is done to remove the resist everywhere except over the source and drain regions, which regions are depressed due to the upwardly protruding gate region and a surrounding upwardly protruding insulating material. The exposed barrier metal is etched away and the remaining resist is stripped, leaving a layer of barrier metal only over the source and drain regions.
    Type: Grant
    Filed: November 30, 1983
    Date of Patent: October 23, 1984
    Assignee: Storage Technology Partners
    Inventors: Jenq-Sian Chang, Yih-Jau Chang
  • Patent number: 4470100
    Abstract: A connector arrangement for making connections between printed circuit boards and connectors located on parallel side panels such as the side panels of a card cage of a computer central processing unit. The printed circuit boards are part of modules which include a retractable connector arrangement. The connectors are moved to a retracted position in which their width is less than the spacing between connectors on the side panels to facilitate their insertion between the side panels. Once in position, the modules are moved to an extended position and connections are made between the modules connectors and those on the side panels. The connectors provide low cost, high reliability, high density connections and facilitate close center-to-center spacings between adjacent modules.
    Type: Grant
    Filed: December 21, 1981
    Date of Patent: September 4, 1984
    Assignee: Storage Technology Partners
    Inventors: Amadeus P. Rebaudo, Art J. Gwerder, William C. Chow, Stimson F. Ho
  • Patent number: 4442361
    Abstract: A system and method for calibrating scanning beam systems, such as electron beam systems, so that a plurality of such systems are compatible one with another, thereby allowing an object that is scanned on one system to be transferred to another system while still maintaining proper alignment between the pattern(s) scanned on the object by one system and the pattern(s) scanned on the object by another system. A calibration plate, having an array of calibration marks thereon at prescribed locations, is made on a first system. This plate is then transferred to a second system where the location of the calibration marks is measured. The measured locations are fitted mathematically to the prescribed locations in order to minimize error. Nonetheless, some error will be present due to the slight misalignments and nonlinearities, such as mirror distortion, that are present between any two scanning beam systems. This error is determined by comparing the fitted measured locations to the prescribed locations.
    Type: Grant
    Filed: September 30, 1982
    Date of Patent: April 10, 1984
    Assignee: Storage Technology Partners (through STC Computer Research Corporation)
    Inventors: John Zasio, Larry Cooke, Raymond Paul
  • Patent number: 4414480
    Abstract: A CMOS output circuit for an integrated circuit chip used in high speed computers is designed so that it can drive transmission line interconnects to thereby increase the speed of the transfer of signals between chips. The CMOS circuit can drive either a nonterminated transmission line, a terminated transmission line or a random wire. The output circuit enables both low power consumption and high speed to be achieved.
    Type: Grant
    Filed: December 17, 1981
    Date of Patent: November 8, 1983
    Assignee: Storage Technology Partners
    Inventor: John J. Zasio