Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: A hybrid lens with a high numerical aperture is described. The hybrid lens comprises a refractive surface that refracts incident light and a diffractive surface that diffracts light exiting the lens, the diffracting surface designed by a sag satisfying the following Equation: s ? ? ? a ? ? ? g = f D + m ? ? ? ? - f D ? ? 2 + r ? ? 2 n - 1 , wherein fD is a distance from a center peak to a focal point of the hybrid lens, r is a height from a center axis to each peak of the hybrid lens, n is the refractive index of the hybrid lens, ? is the wavelength of incident light and m is an integer. The hybrid lens is small and lightweight and capable of removing chromatic aberration.

Abstract: A scene change detector includes first and second frame buffers individually storing two image frame data to detect a scene change, a first and a second color space conversion units converting the image frame data stored in the first and second frame buffers into predetermined first and second color signals and outputting the first and second color signals to first and second histogram detection units, respectively, first and second histogram detection units calculating histograms from the color signals converted at first and second color space conversion units, a cross correlation coefficient calculation unit calculating a correlation value between a first histogram calculated at the first histogram detection unit and a second histogram calculated at the second histogram detection unit, and a decision unit outputting a scene change signal by comparing a value calculated at the cross correlation coefficient calculation unit with a predetermined threshold.

Abstract: A wet electro-photographic printer includes a transfer/fixing apparatus having a subsidiary intermediate transfer unit disposed to contact a transfer belt to re-transfer an image on a printing paper after receiving the image from a transfer belt, a back-up unit disposed to contact the subsidiary intermediate transfer unit through the printing paper in order to transfer the image transferred to the subsidiary intermediate transfer unit to the printing paper, and a fixing unit fixing the image simultaneously or separately when the image transferred to the subsidiary intermediate transfer unit is re-transferred to the printing paper. The transfer belt includes a single non-elastic layer made of one material selected from polyimide, polycabonate and ethylene-tetrafluoroethylene.

Abstract: For use in a switch comprising N call application nodes (CANs), a method of upgrading call process server applications that comprise a primary call process and a backup call process executed on different CANs.

Abstract: A photosensitive polymer comprises a fluorinated ethylene glycol group and a chemically amplified resist composition including the photosensitive polymer.

Abstract: Disclosed is a transmissive and reflective type LCD. In the LCD, a second substrate faces a first substrate. A liquid crystal layer is formed between the first substrate and the second substrate. A first polarizing plate is formed on an outer surface of the first substrate. A second polarizing plate is formed on an outer surface of the second substrate. A backlight is arranged for irradiating incident light onto the polarizing plate. A transparent transflective film is arranged between the first polarizing plate and the backlight for partially reflecting and partially transmitting the incident light. The transparent transflective film includes at least a first layer and a second layer, the first and second layers having different refractivity indexes from each other and are alternatively stacked.

Abstract: A portable computer having a main board; an antenna receiving and transmitting an RF signal; a PCI slot part provided in the main board and receiving the RF signal received and transmitted through the antenna; a wireless LAN card including a main card removably inserted into the PCI slot part, and an RF connector provided at a side of the main card and through which the RF signal is inputted/outputted between the antenna and the PCI slot part; and an antenna connecting part connected to the RF connector and allowing the RF signal to be inputted/outputted through the RF connector between the antenna and the PCI slot part when the wireless LAN card is inserted into the PCI slot part. With this configuration, the present invention provides a portable computer improved in a mounting structure of a wireless LAN card doing not have an antenna.

Abstract: A method and a host for allocating a plurality of Internet Protocol (IP) addresses to a Network Interface Card (NIC) which has a unique Media Access Control (MAC) address comprising vendor code and serial code is provided. The method for allocating multiple IP addresses to the NIC in a host includes: setting up a virtual MAC address by combining a virtual vendor code and a serial code; mapping the virtual MAC address with one of internal addresses of actual IP addresses allocated to a host; and allocating the mapped internal address and the virtual MAC address to an application that requests an IP protocol. Since a plurality of IP addresses can be allocated to one NIC in the IP address allocation method, as many NICs as required IP addresses are not necessary and cost-effectiveness can be achieved.

Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o

Abstract: Disclosed is a nonvolatile semiconductor memory device having a memory cell array by which random access can be performed. The memory cell array structure of the nonvolatile semiconductor memory device having a main memory cell array formed of a plurality of NAND cell strings includes a sub memory cell array having a plurality of NAND cell strings that is provided therein with memory cell transistors. The number of the memory cell transistors in the sub memory cell array is less than that of the memory cell transistors in the NAND cell strings of the main memory cell arrays. The sub memory cell array is operationally connected to main bit lines of the main memory cell array during program and erase operations and is electrically disconnected with the main bit lines during read operation, thereby having a separate read path that is independent from the read path of the main memory cell array.

Abstract: The present invention provides a semiconductor memory cell repairing apparatus and method that can effectively repair memory cells although a various type of failures in memory cells are generated when a rule in the failure is detected.

Abstract: An address generating circuit of a semiconductor memory device includes address buffers, multiplexers, shift registers and latches by which high-bit and low-bit write/read addresses in a normal mode and in a burst mode are routed through separate paths. A control circuit routes the high-bit read address data through a different path than the high bit write address data. The paths are joined to a common output latch, and include differential delays for the data. Similarly, the low-bit read continuing burst address data is routed through a different path than the low bit continuing burst write address data.