Abstract: A circuit that performs a prefix computation. This circuit includes an N-bit prefix network of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ?, such that, Y1=X1, Y2=X2?X1, Y3=X3?X2?X1, . . . , and YN=XN?XN?1? . . . ?X2?X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2t horizontal wiring tracks between each logic level. Additionally, l+f+t=L?1, and unlike existing prefix circuits, 1>0,f>0, and t>0.

Abstract: A system and method for adding routing information for a node to a routing table, which efficiently makes necessary changes to the routing table to support routing to and from the node, while maintaining the deadlock-free quality of the paths described by the routing table. The routing table is generated by storing routing information in the routing table that reflects and describes a deadlock-free set of paths through a network of nodes. A row of entries is added to the routing table describing how to forward data units from the node. A column of entries is added to the routing table describing how to forward data units addressed to the node. The forwarding information within each entry added to the routing table maintains the deadlock-free quality of the set of paths represented by the forwarding table.

Abstract: A metadata-aware Enterprise Application Integration (EAI) framework for an application server environment. The framework allows the connector writer to connect to a system using a low-level API. The framework provides a space in a connector in which to define high-level functions. Using the framework, the user can mine metadata for the functions and generate a description of each high-level function that can be dropped into the framework and appear as a high-level function invokable through the connector. This high-level function manifestation, when invoked, drives the low-level API provided by the connector. An adaptive layer may wrap a native Common Client Interface (CCI) exposed by a connector to provide an abstract connector that allows a higher-level abstraction of external Enterprise Information Systems (EIS). The adaptive layer may interpret metadata to model an external EIS as a logical data source. The adaptive layer may be referred to as a metadata-aware CCI adapter.

Abstract: A system and method for predicting whether a dynamic reconfiguration of a resource of a resource domain would be successful, prior to attempting the reconfiguration. A resource domain includes one or more computer resources (e.g., physical, logical and pseudo devices) and a graph management agent configured to maintain a graph representing the resources and dependencies between resources. Vertices of the graph represent resources; edges represent dependencies. A resource domain may also include a set of policies or constraints regarding resources and reconfigurations of resources. An illustrative constraint may specify that a particular resource (e.g., a multi-pathed logical device) must have a minimal number of paths (e.g., two). The graph agent identifies the effect the dynamic reconfiguration operation would have upon the resources and dependencies, and determines whether any constraints would be violated.

Abstract: A system and method for determining a structure within a software kernel using an offset and an element is disclosed. The software kernel is received from a third party for debugging operations. Given one or more element and offset pairs, data extracted from the software kernel is searched to produce a list of possible structures to provide additional information during the debugging operations. The data is extracted into tables with symbol table information. The symbol table information is searched using an offset and an element. Structures are identified using this information and, optionally, a structure size may be provided to further limit the possible structures.

Abstract: Disclosed is a system having a power input line. A power supply facility provides the system with a combined set of signals including a power signal and a status signal over the power input line. Additionally, disclosed is a system having at least two power input lines. Uninterruptible power supply facilities provide the system with combined sets of signals including a power signal and a status signal over the power input lines. Each combined set of signals includes a unique UPS identifier, which can be used to determine whether power sources for power input lines are unique.

Abstract: Dedicated federated beans monitor an event service in a data services management system and sends human-readable messages to people involved in the administration of management services in order to inform the administrators that an event they are interested in has occurred. In one embodiment, the beans each contain a category list indicating which events are of interest to the administrators and the beans cooperate with each other to insure that the category lists in the beans are synchronized. In another embodiment, the federated bean composes and forwards e-mail messages to administrators. In still another embodiment, the federated bean also monitors and reports messages posted to a logging service.

Abstract: A computer generated document file comprises content data and template data including, for example, formatting information. The size of the document file is reduced by removing unused and/or duplicate template data.

Abstract: A shape-based geometric database uses R-trees to compactly and efficiently represent design objects. Such R-trees may be populated in an efficient and balanced manner to improve the efficient use of such R-trees in various stages of circuit design, for example. For example, tiles are assigned to bins depending at least partially on orientation of the tiles and on proximity of the tiles to reference tracks having similar orientations. Bin R-trees may be defined, along with direction and layer R-trees using a level sequential process from lower levels to higher levels until a root node is defined in each case.

Abstract: Cache access is optimized through identifying redundant accesses (read-requests made to identical system memory addresses), and issuing a single cache data request for each group of redundant accesses. One embodiment of the invention is a graphics system comprising a system memory that stores texture data, coupled to a texture cache that is coupled to one or more texture pipes. Each pipe processes information for a respective spatial bin. A cache preprocessor receives read-requests for texels from the texture pipes and generates a control code corresponding to each read-request, indicating whether the read-request is a redundant access, and linking redundant accesses to a single cache data request. The cache preprocessor provides the control codes and the read-requests to a cache arbiter, which issues the codes and the cache data requests to the texture cache.

Abstract: A method and apparatus for generating a CRL with a last_changed extension. When sequential CRLs are generated there is the potential that there will be no changes in the data associated with the CRL. In this case a recipient of the new CRL may needlessly perform processing on the new CRL. A CRL consistent with embodiments of the present invention provides an extension to specify the CRL number of the last_changed CRL. This provides the recipient with information to determine whether the new CRL should be processed or the existing data is up to date.

Abstract: A method and apparatus for performing fast clip-testing operations in a general purpose processor are provided. This is accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and whether x-is less than negative y. The values x and y are stored in respective source registers of the processor specified by the instruction. Finally, as a result of the determination, one or more binary values representing the results of the determination are inserted into a destination register of the processor also specified by the instruction. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute a clip-testing function with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function.

Abstract: One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.

Abstract: A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information into internal bridge registers that control the flow of information between bus segments. The configuration host also populates an address bitmap in each bridge in order to complete the bus system configuration. In one embodiment, the bus topology is a tree configuration and the configuration host performs a recursive procedure that configures each branch of the tree. During this configuration process the internal bridge registers and address bitmap in each bridge are populated.

Abstract: A method for handling different versions of a document in a computer system comprising a storage medium includes storing each of the different versions in its entirety in a file on the storage medium.

Abstract: Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.

Abstract: An enhanced VPD structure includes a type field to indicate whether a particular property is a general property to be associated with an interface card or other computer system component, or a device- or function-specific property to be associated with one or more devices or functions. The enhanced VPD structure also includes fields for identifying the device(s) and/or function(s) to which a device- or function-specific property applies, along with the value of the property, a data type and length of the property, and a meaningful name of the property. The enhanced VPD structure may be accessed during system boot, during hot-swapping of an interface card or other component, or at other times.

Abstract: The data type of requested data stored in a column of a database table is determined and the data accessed in the data type in which the data is stored. The data type can then be converted to a second data type before outputting the data.

Abstract: A method and apparatus for generating bits for a diagnostic routine of a memory subsystem. A memory device may be divided into n subdivisions of m bits each. Alternatively, n memory devices may each have m bits (in width). The system may also have a cache line having a certain number of check words. A diagnostic routine may begin with the generating one of 2m bit patterns and assigning m bits of the generated bit pattern to one of the check words in the cache line. Each of the m bits assigned to the check word in the cache line may have the same logic value. However, each bit of the n subdivisions may be associated with a different check word in the cache line with respect to other bits of the subdivision. The method may be repeated for each of the 2m bit patterns that may be generated.

Abstract: A registration and authentication scheme that may be used in conjunction with a computer-based system for monitoring other computer systems is disclosed. A monitored relay transmits a unique identifier to a server in the monitoring system. The server generates a random number pair, ensures the random number pair is unique, and associates the unique relay identifier with the random number pair to form an unbound key, which is registered in a database associated with the server. The unbound key is encrypted and made available to the relay. Subsequently, when the relay is instantiated it transmits the contents of the unbound key file to the monitoring system. The monitoring system decrypts the unbound key file and searches associated databases to determine whether the relay is registered and authenticates the relay.