Abstract: The present invention describes a method and system for managing high-availability-aware components in a networked computer system. In particular, the method includes registering components and dynamically allocating roles and assignments to one or more of the registered components to achieve a desired level of redundancy based on component type information. The method may include an additional step of performing administrative actions on the registered components in response to a request from an external management agent in order to increase the availability of services provided by the high-availability-aware components. Further, the method may additionally include responding to an error by changing roles and assignments of one or more of the registered components, providing information to registered components so that related components may communicate to achieve a desired redundancy level, and/or maintaining additional information relevant to managing high-availability-aware components.

Abstract: One embodiment of the present invention provides a system and method for appending server-side glossary definitions to transient Web content in a networked computing environment. A glossary database stores a glossary, which includes a plurality of structured records. Each structured record is keyed by a unique identifier derived from a key word and contains a definition associated with the key word. A parser receives Web content, which includes text in transit to a Web client, and parses the text into one or more tokens corresponding to one such key word. A comparator module matches the tokens against each unique identifier in the glossary and retrieves each structured record containing a matching unique identifier. A constructor inserts a hyperlink in place of the text corresponding to each matched token and references the definition contained in the retrieved structured record for the matching unique identifier.

Abstract: A testing harness for a design-under-test is modified to include a standalone implementation of an application programming interface used in developing the design-under-test. The standalone implementation is adapted to a target device, and is packaged with an executable application or MIDlet, together with any needed resource files. Either the package, or optionally a JAR and JAD file, is downloaded to a remote user for execution on the target device. Using the application programming interface and the other downloaded files, the remote user can test the target device, analyze the results, and even modify the test conditions without recourse to the testing harness. The arrangement provides a capability for a party who is not privileged to know details of the testing harness to practically evaluate and modify the design-under-test using a standalone testing application.

Abstract: A method for submitting a bug report utilizes a bug submission module to request a bug submission service from a first support host using a Support Interface Module for communicating with the first support host. The bug submission service includes a list of data to be collected and the return address of a second support host. The first support host also includes a support services resource. The bug submission module receives the requested bug submission service from the first support host using the Support Interface Module and collects data based on the list of data to be collected. The bug submission module then sends the collected data to the return address of second support host using the Support Interface Module.

Abstract: A method for managing constant values among disparate code portions that use the same constant names is provided. The method includes inspecting the disparate code portions to identify constant names used in the disparate code portions and defining name value pairs in a text file. The method then includes parsing the text file. The parsing of the text file is configured to generate a definition code file for each of the disparate code portions, and each of the disparate code portions has an associated definition code file, and the associated disparate code portion and definition code file have the same language type. Further, each definition code file defines a same constant value for the same constant names used in each of the disparate code portions.

Abstract: An apparatus and method for managing the receipt of communication traffic in the form of packets or other units. The apparatus includes a communication interface (e.g., a NIC, a TCA) coupled to one or more host computer systems. Through Direct Memory Access (DMA) operations, the interface reassembles payloads of received packets into host buffers based on their sequence numbers, without buffering them in the interface. Packet headers are separated from the payloads and passed to a host for protocol processing after the payload DMA is completed. Host buffers may be of virtually any size. For each communication connection, state information is maintained on the interface, which may identify an upper level protocol so that an upper level protocol header is passed to the host as part of the packet header, not as part of the payload. Protocol termination remains in the host.

Abstract: A simulator running on a single computer may be configured to appear as one or more users simultaneously initiating Internet requests from separate user environments using a plurality of different authentication methods. An engine of the simulator may communicate with a browser to appear as one or more users each having access to a local defined user account and initiating Internet requests using the plurality of different authentication methods. The simulator may be configured to maintain different user profile data for each user appearing to operate within a separate user environment. The simulator may be configured to appear as one or more separate users initiating Internet requests using a plurality of different authentication methods from multiple, different user environments.

Abstract: A system and methods are provided for inserting probe points into an executing program, and measuring the time spent traversing code paths from one probe point to any other probe point or some other performance metric (e.g., instructions executed, cache misses, memory addresses accessed). One method is implemented by inserting N probes. Each probe has a corresponding function configured to: retrieve the identifier and timestamp of the previous probe executed, calculate the time spent traversing the path from the previous probe to the current probe, and update a matrix of N×N elements, wherein each element corresponds to a path from one probe to another probe. After completion of the program, this matrix is useful for identifying code paths that are bottlenecks and hence candidates for optimization.

Abstract: The preferred embodiments relate to a system and method for creating an end-to-end e-business system for an enterprise. In some embodiments, a strategic architecture roadmap includes: a) an upper infrastructure layer having a service-driven architecture, with a virtual application layer having a distributed component architecture, and with a an application infrastructure layer having an n-tiered architecture; and b) a lower infrastructure layer having a network-centric architecture, with a compute server infrastructure layer having an adaptive compute architecture, and with a data storage infrastructure layer having a storage network architecture.

Abstract: An apparatus for enhancing the speed of a synchronous bus includes a two register based FIFO with software control bits and a second clock signal. According to the invention, the second clock signal rd_clk is supplied by the same PLL that provides the main clock signal lg_clk. According to the invention, data is taken from the two registers in alternative clock cycles so that each of the register holds valid data for two clock cycles. A first software data bit is used to determine which of the two registers is unloaded first. Using the method and structure of the invention, the window for transferring valid data is increased and therefore the system employing the method and apparatus of the invention is more skew tolerant.

Abstract: A garbage collector employs the train algorithm to collect a heap generation incrementally, collecting “car sections” in a collection order. As it updates the “remembered sets” by which it keeps track of where references to objects in respective car sections are located, it also updates oldest- and youngest-car indicators for each car section. The oldest- and youngest-car indicators for a given car section specify limits in the collection sequence beyond which references to objects in the given car have not been found. The garbage collector uses these indicators to identify cars that contain no objects that are reachable except through a reference chain that includes the collection set for the current collection increment. It adds one or more such cars to the collection set, and it collects the thus-expanded collection set without processing the remembered sets associated with the added cars.

Abstract: One embodiment of the present invention provides a system that facilitates prefetching memory pages for a computer program. The system operates by analyzing the computer program within a compiler to identify memory pages accessed within a portion of the computer program. Next, the system creates a map of these memory pages accessed by the computer program, wherein the map is indexed by a program counter for the computer program. A given program counter value indexes memory pages within this map that are likely to be accessed during subsequent execution of the computer program. The system examines the map during execution of the computer program, and if the current program counter for the computer program indexes memory pages in the map, the system touches the memory pages, thereby causing the system to prefetch the memory pages.

Abstract: Where there are potentially two or more applications installed on a smart card, with each application having a stored application identifier (AID), a desired application may be selected by specifying a desired application in terms of multiple parameters, retrieving multiple parameters from a stored AID for an application on the smart card, and comparing the specified multiple parameters with the retrieved multiple parameters to determine whether there is a match.

Abstract: A method for analyzing a target system, that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is defined in a characteristics model and each of the plurality of characteristics is associated with one of a plurality of artifacts defined in the characteristics model, storing each of the plurality of characteristics in a characteristics store, and analyzing the target system by issuing a query to the characteristics store to obtain an analysis result, wherein the query is used to determine the presence of a first pattern in the target system.

Abstract: A method for analyzing a target system that includes obtaining a characteristics model, loading the characteristics model into a meta model, obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein each of the plurality of characteristics is associated with the characteristics model, storing each of the plurality of characteristics obtained from the target system in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result, wherein the issuing the at least one query comprises verifying the at least one query using the meta model.

Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store using a tracking mechanism, and analyzing the target system by issuing a query to the characteristics store to obtain an analysis result, wherein the query uses tracking information associated with the tracking mechanism.

Abstract: A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor, wherein the plurality of characteristics is associated with a characteristics model, storing each of the plurality of characteristics in a characteristics store, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result.

Abstract: A method for analyzing a target system that includes obtaining a characteristics model, generating at least one selected from the group consisting of a schema, characteristics store API, and a characteristics extractor, using the characteristics model, obtaining a plurality of characteristics from the target system using characteristics extractor, wherein each of the plurality of characteristics is associated with the characteristics model, storing each of the plurality of characteristics in the characteristics store using the schema, and analyzing the target system by issuing at least one query to the characteristics store to obtain an analysis result.

Abstract: A processor includes a set of registers implemented internal to the processor and plural virtual registers. The set of registers are each individually addressable using a corresponding register identification and the plural virtual registers are each individually addressable using a corresponding virtual register identification. At least one of the virtual registers is an auxiliary register implemented internal to the processor. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation.

Abstract: Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the performance on any processors is provided. In particular, the rules of instructions scheduling for the machines of interest of different processors are abstracted. From the abstractions, a hypothetical machine is generated that is the restrictive or constraining set of the actual machines modeled in the abstraction step. After generating the hypothetical machine, the restricted hypothetical machine is targeted rather than the actual machines modeled in the first step. Thereafter, conflicts, if any are resolved by modeling the performance impact and selecting the less damaging choice.