Abstract: A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog® is generated for the evaluate phase of a dynamic circuit. Second, “comment-logic” in Verilog® syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the “clk=0” and the “clk=1” conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art.

Abstract: A method and system for web based control components. Specifically, the present invention describes a method of rendering user interface button and tab control components within a hypertext markup language (HTML) web page. The present invention generates an HTML table that comprises a plurality of cells. For a button component a two row by three column table is generated. For a tab component a five column table is generated. The present invention places a plurality of graphical corner images in the plurality of cells to produce corner outlines of the button or tab control component. Multiple button or tab components can be coupled together in a single table by repeatedly adding more of the plurality of cells associated with button or tab components, respectively. In addition, the control component has the ability to accommodate word wrapping of the text contained within the control component.

Abstract: An invention is provided for generating custom clock frequencies within a processor core. A CPU clock signal propagates through a DLL circuit. Further, a control signal controls the CPU clock signal as the signals propagate through multiple inverters in the DLL circuit. The multiple inverters delay the CPU clock signal and generate multiple output signals. Subsequently, the multiple output signals are combined to generate a higher frequency signal than the CPU clock signal. To control the CPU clock signal, the DLL circuit includes a charge pump to lock in a precise control signal. The charge pump further includes circuitry, such as a Schmitt circuit, to increase and decrease voltage.

Abstract: A telephone set is modified to permit it to automatically send repetitive data associated with telephone purchases. A retailer and a customer interact to ensure that accurate data is initially stored while eliminating the necessity of repeating the same information during subsequent purchases. A removable portable device stores the same information and permits a user to make purchases from any telephone.

Abstract: A method and apparatus for decoding signals received from a network and distributing the decoded signals to multiple users. A bulk decoder coupled to a network decodes data received from the network and transmits the decoded data to an interconnect for distribution to a plurality of users. The number and type of bulk decoders may be adjusted in accordance with system load.

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction.

Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.

Abstract: Diagnosis of corruption in interrelated data entities uses a graph of nodes and edges. Datum nodes represent the data entities, relationship nodes represent the relationships among the data entities. The datum nodes are connected through their relationship nodes by the edges. When corruption is detected, the relationships are analyzed and each edge connecting a datum node to a relationship node is removed from the graph when the corresponding relationship is invalid. The datum nodes that remain connected to their relationship nodes form a subgraph and the corresponding data entities are considered correct. In one aspect, if more than one subgraph is formed, the datum nodes in the largest are used. In another aspect, the data entities and relationships are analyzed to create the graph when the data entities are assumed correct. The data entities may be data and metadata of various types that can be associated with the data.

Abstract: Disclosed are novel methods and apparatus for efficiently providing critical path analysis of a design. In an embodiment, an apparatus disclosed can assist in creating a single critical path schematic which can be used to simulate both rising and falling edge delays. This saves time as only one schematic and one simulation is required instead of the two generally required.

Abstract: A method of providing accelerated post-silicon testing for a silicon hardware includes computing a simulation cumulative record of state using a plurality of test instructions and a cycle breakpoint, performing a simulation of an instrumented logic design using the plurality of test instructions and the cycle breakpoint, manufacturing the silicon hardware using the instrumented logic design, computing a silicon cumulative record of state by executing the plurality of instructions using the silicon hardware; and comparing the simulation cumulative record of state to the silicon cumulative record of state.

Abstract: A processor avoids or eliminates repetitive replay conditions and frequent instruction resteering through various techniques including resteering the fetch after the branch instruction retires, and delaying branch resolution. A processor resolves conditional branches and avoids repetitive resteering by delaying branch resolution. The processor has an instruction pipeline with inserted delay in branch condition and replay control pathways. For example, an instruction sequence that includes a load instruction followed by a subtract instruction then a conditional branch, delays branch resolution to allow time for analysis to determine whether the condition branch has resolved correctly. Eliminating incorrect branch resolutions prevents flushing of correctly predicted branches.

Abstract: A system and method are disclosed for rendering polygons. Parameter values may be rendered for only one sample position of a plurality of neighboring sample positions within a polygon. The parameter values rendered for the one sample position may then be transmitted to one or more memories and conditionally stored in a plurality of memory locations that correspond to the plurality of neighboring sample positions. Transmitting parameter values to one or more memories may be achieved in a single transaction. Depth values may be rendered for each sample position in the plurality of neighboring sample positions. Depth value data may be compressed. In some embodiments, the one or more memories may be configured to determine depth values for each of the neighboring sample positions.

Abstract: A storage system including hierarchical cache metadata storages includes a cache, a first metadata storage, and a second metadata storage. In one embodiment, the cache may store a plurality of data blocks in a first plurality of locations. The first metadata storage may include a plurality of entries that stores metadata including block addresses of data blocks within the cache. The second metadata storage may include a second plurality of locations for storing metadata including the block addresses identifying the data blocks within the cache. The metadata stored within the second metadata storage may also include pointers to the data blocks within the cache. The cache and the first metadata storage are non-volatile storages. However, the second metadata storage may be a volatile storage.

Abstract: Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.

Abstract: An interconnect system connects two drawers of a redundant computer system, wherein each drawer contains a redundant node of the computer system. A first signal source and a first signal preventer are operatively associated with a first drawer of the two drawers. A second signal source and a second signal preventer are operatively associated with a second drawer of the two drawers. Each of the two drawers has a connection interface that includes a plurality of terminals connected to a redundant node of the drawer. A redundant system may be provided by connecting the connection interfaces with a connector. The connecter is further configured to connect the first signal source to the second signal preventer, and the second signal source to the first signal preventer, thereby signaling each drawer that the computer system may be operated in a redundant mode.

Abstract: A method for generating a code bridge between a client application and a target application, including generating a metadata file defining exposed interfaces for the client application and the target application, creating a schema defining the code bridge using the metadata file, and generating source code for the code bridge using the schema.

Abstract: An apparatus and method for facilitating development of Java Embedded Server bundles which includes a module containing a set of development tools used in the creation of Java Embedded Server bundles. The module may include a code template tool having sample code segments; a Java Embedded Server manifest generator tool that creates Java Embedded Server manifest files for Java Embedded Server bundles; a Java Embedded Server jar packager tool that packages Java Embedded Server bundles; and a web page link tool having links to Java Embedded Server-related web pages.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: A storage system includes a cache and a collection of metadata, organized by their associations with regard to the data they represent. In one embodiment, the cache stores data blocks in a first plurality of locations. A first metadata storage stores metadata including block addresses of data blocks within the cache. A second metadata storage includes a second plurality of locations, each for storing metadata including a block address identifying a corresponding data block within the cache. The metadata stored within the second metadata storage also includes a first pointer to the corresponding data block. In addition, at least one of the second locations may store a second pointer to another of the second locations that stores metadata corresponding to a related data block. The cache and the first metadata storage are non-volatile storages; however, the second metadata storage may be a volatile storage.

Abstract: An indicator assembly for a computer system can comprise a light guide for directing light from an indicator light source to an exterior panel of the computer system. The assembly can also comprise a photodetector configured to receive a portion of the light transmitted by the light guide. The photodetector can produce a signal representative of the portion of light received. For example, the photodetector may produce a signal representative of the color and/or intensity of the portion of light received. Using the signal representative of the portion of light received, components such as a controller can test for the presence of faults.