Abstract: A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips.

Abstract: A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register for storing an access count, a low threshold register for storing a low threshold, and a high threshold register for storing a high threshold. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action.

Abstract: A system for proximity communication between semiconductor chips includes a package assembly. The package assembly includes a plurality of bridge circuits made of organic or plastic semiconductor material. A plurality of base chips are assembled to the package assembly. The package assembly positions and aligns the plurality of base chips such that the bridge circuits bridge the base chips and enable proximity communication between the base chips.

Abstract: A system for conducting a conference call based on a community document. The system includes a data network, a first conference client device and a second conference client device communicatively coupled to the data network, wherein the first conference client device is associated with a first user of the conference call and the second conference client device is associated with a second user of the conference call, and a conference server device communicatively coupled to the data network.

Abstract: A device list is created for an operating system and/or a virtualized operating system. A bus node is created for each bus. Interface nodes are created as child nodes of the respective bus and a status indicator indicates whether a device connected to the interface is accessible. A device node is created for the device connected to the interface. Virtualized interface nodes are created as child nodes of the device node for each virtual device included in the device and a status indicator indicates whether the respective virtual device is accessible. Then, devices and/or virtual devices may be added and/or removed utilizing the list. After a device and/or virtualized device has been removed for one operating system and/or virtualized operating system, it may then be added to another. In this way, devices and/or virtualized devices can be virtually hot plugged without physically connecting and/or disconnecting devices.

Abstract: Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage.

Abstract: Disclosed herein are aspects of optical tape technology, tape manufacturing, and tape usage.

Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.

Abstract: A processing unit executes a vector width instruction in a program and the processing unit obtains and supplies the width of an appropriate vector register that will be used to process variable vector processing instructions. Then, when the processing unit executes variable vector processing instructions in the program, the processing unit processes the variable vector processing instructions using the appropriate vector register with the instructions having the same width as the appropriate vector register. The width that the processing unit obtains may be less than an actual width of the appropriate vector register and may set by the processing unit. In this way, many different vector widths can be supported using a single set of instructions for vector processing. New instructions are not required if vector widths are changed and processing units having vector registers of differing widths do not require different code.

Abstract: Some embodiments of the present invention provide a system that facilitates the operation of a supercapacitor. During operation, the system measures an electrical parameter of the supercapacitor using a set of conductor rings surrounding a capacitor seal of the supercapacitor. Next, the system determines the presence of a leak in the supercapacitor based on the electrical parameter. Finally, the system manages the operation of the supercapacitor based on the presence of the leak.

Abstract: One embodiment provides a system that prevents duplicate entries in a non-blocking TLB that supports multiple page sizes and speculative execution. During operation, after a request for translation of a virtual address misses in the non-blocking TLB, the system receives a TLB fill. Next, the system determines a page size associated with the TLB fill, and uses this page size to determine a set of bits in the virtual address that identify the virtual page associated with the TLB fill. The system then compares this set of bits with the corresponding bits of other virtual addresses associated with pending translation requests. If the system detects that a second virtual address for another pending translation request is also satisfied by the TLB fill, the system invalidates the duplicate translation request associated with the second virtual address.

Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.

Abstract: The present disclosure provides a compiler prespill phase that reduces or eliminates excessive register pressure, or locations in the code of a program where live virtual registers exceeds physical registers of a target computing device, prior to register allocation. The prespill phase identifies points of excessive register pressure, selects candidate virtual registers, chooses virtual registers to prespill from the candidates, and inserts spill and reload instructions to prespill the chosen registers. The prespill phase may reduce the register pressure such that the live virtual registers only exceed the physical registers by a particular number, the live virtual registers equal the physical registers, or the physical registers exceed the live virtual registers by a particular number. The compiler may then perform one or more early and/or late instruction scheduling phases, including global and/or local instruction scheduling, to optimize the placement of the spill and reload instructions.

Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.

Abstract: Methods and apparatus are provided for managing classification of packets within a multi-function input/output device, and for allowing the device's classification tables to be cleared in a non-blocking manner. The input/output device conveys multiple communication connections corresponding to multiple physical and/or virtual PCIe (Peripheral Component Interconnect Express) functions bound to software images executing on hosts. The device comprises gate logic configured to indicate statuses of the functions or the DMA engines bound to the functions. When the gate logic indicates a particular destination function is valid, the packet is transferred normally after being classified. A portion of the logic corresponding to a given function is reprogrammed to indicate the function is invalid when that function is reinitialized (e.g., FLR or Function Level Reset). The function's entries in packet classification tables are cleared afterward.

Abstract: A method for performing garbage collection promotion, comprising determining that an age of a large young object is greater than a predetermined tenuring threshold, wherein the predetermined tenuring threshold specifies an age beyond which objects are promoted, setting a plurality of types of a plurality of large memory regions from young to old to promote the large young object to a large old object, wherein the plurality of large memory regions host the large young object, scavenging references of the large old object, wherein the large old object is a large promoted object, scanning a large young object list to identify a plurality of unvisited large young objects, wherein a plurality of visited bits of the plurality of unvisited large young objects are unset, and releasing a plurality of unvisited large memory regions, wherein the unvisited large memory regions host the plurality of unvisited large young objects.

Abstract: The described embodiments provide a processor (e.g., processor 102) for executing instructions. During execution, the processor starts by transactionally executing instructions from a protected section of program code. The processor then encounters a transactional failure condition while transactionally executing the instructions from the protected section of program code. In response to encountering the transactional failure condition, the processor enters a transactional-scout mode and speculatively executes subsequent instructions in the transactional-scout mode.

Abstract: A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data.

Abstract: Some embodiments provide a system that analyzes telemetry data from a computer system. During operation, the system obtains the telemetry data as a set of telemetric signals from the computer system and validates the telemetric signals using a nonlinear, nonparametric regression technique. Next, the system assesses the integrity of a power supply unit (PSU) in the computer system by comparing the telemetric signals to one or more reference telemetric signals associated with the computer system. If the assessed integrity falls below a threshold, the system performs a remedial action for the computer system.