Abstract: Methods and apparatuses are disclosed for improving the speed of chip routing for integrated circuit blocks with multiple connections. In some embodiments, the method may include creating a layout abstract for a first block and a second block of the integrated circuit, where the first and second blocks are coupled together via a plurality of connections. The method may further include determining whether the number of connections in the plurality exceeds a threshold, and in the event that the number of connections exceeds the predetermined threshold, representing a first subset of the plurality as a first logical connection.

Abstract: A system for rendering a web page is disclosed. The system comprises a server adapted to communicate with a client. The client operates a browser in communication with the server and is arranged to render material to the browser that an end user may view on the web page. The system also includes a dynamic code set having configuration parameters for use in rendering the web page, wherein the configuration parameters are formed of a first configuration parameter including at least one of combined resources, strategically placed resource tags, headers set to ensure cacheable resources, a GZip file, and minified resources, and a second configuration parameter including at least one of combined resources, strategically placed resource tags, headers set to ensure cacheable resources, a GZip file, and minified resources. A method of creating a web application is disclosed. A machine readable medium is also disclosed.

Abstract: A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used.

Abstract: A system, including a computing device, performs a method for communicating with a message service via a file system interface. A file system driver receives a file system call from an application program executing on the computing device. The file system driver converts the received file system call into a message service request. The file system driver transmits the message service request to a message service server. The message service server processes the message service request and generates a response to the message service request. The message service server then sends the message service response to the file system driver. The file system driver converts the received message service response into a file system call response. The file system driver may return the file system call response to the application program or may store the file system call response as a file system file in a file system.

Abstract: A flip-flop or other state circuit that includes level-shifting functionality. In connection with a flip-flop, embodiments include an inverter circuit element that has a data input line as its input and a data complement line as its output. The inverter resides in voltage domain that is lower than the voltage domain associated with remainder of the flip-flop.

Abstract: A system includes an input device, an output device, a printed circuit board, and a semiconductor device. The semiconductor device includes a semiconductor die. The semiconductor die includes a clock distribution network that distributes a primary clock signal. The clock distribution network includes a low RC local clock distribution structure. The low RC local clock distribution structure includes a conductor, a first clock signal incident on the conductor, a local gain buffer pair that receives the first clock signal and outputs a second clock signal corresponding to the first clock signal, and a shorting bar that shorts the second clock signal to a plurality of conductors.

Abstract: A computer adapted for force-air cooling of a processor. The computer includes a board supporting the processor and a heat sink mounted such with its base plate contacting the processor. A primary mount supports the heat sink near the processor, and a portion of the heat sink base plate extends outward a distance or overhang length from the primary mount to an edge. The apparatus includes a secondary heat sink mounting assembly supported upon the processor board that includes a damping element with an resilient body positioned proximate to the edge of the base plate, whereby the body abuts the base plate during movement of the base plate toward the board, e.g., upon application of a dynamic or shock load that causes the overhanging portions of the base plate of the heat sink to vibrate or oscillate about the support locations of the primary mount.

Abstract: A method of assigning names to components of a networked computer system is provided. The networked computer system includes at least one modular computer system having at least one service processor module and a plurality of information processing modules removably received in a modular computer system housing. The method comprises: receiving at the service processor module a naming command message including a naming format from a management entity of the networked computer system. The method also comprises assigning at the service processor module a name to the service processor module and to the information processing modules received in the housing in accordance with the naming format; and transmitting a message from the service processor module to a domain name server of the networked computer system, the message including an IP address of each module and the name assigned to each respective module.

Abstract: Implementations of the present invention may involve methods for providing an optical differentiation on a printed circuit board to assist in identifying a missing or improperly mounted component. The optical differentiation may be such that, when a component of the board is missing or improperly attached to the board, a distinct optical difference is created on the board in the visible or non-visible spectrum. Several implementations may create a visible color difference, a non-visible mark, a recognizable shape, texture change, cross hatching or other form of physical modification beneath the component or on the printed circuit board. Other implementations may include the optical differentiation within a silk-screen of the board or on an internal layer of the board.

Abstract: Methods and apparatuses are presented for improving reduced power operations in embedded memory arrays. Some embodiments may include a microprocessor, the microprocessor including at least one execution unit, a memory coupled to the execution unit, the memory including, a memory cell comprising a memory cell bus, a power circuit selectively coupling the memory cell bus to a first power plane and a second power plane, where the memory cell bus is coupled to the second power plane when the power circuit is substantially off, and a bit line pre-charge circuit coupled to the power circuit, where the power circuit selectively couples the first power plane to the pre-charge circuit for a predetermined period of time.

Abstract: The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.

Abstract: A component positioning and securing bracket assembly includes a front rail, a rear rail, and a bottom rail to define a front, a rear, and a bottom boundary of the component positioning and securing bracket assembly. The front rail, the rear rail, and the bottom rail define a structure into which is received the component in a first direction of movement, and a lever provides leveraged motion in a second direction of movement to connect a port of the component to a component connector and to secure the component in the component positioning and securing bracket assembly. The component positioning and securing bracket assembly is in an array of a plurality of components, in which any one component can be installed or removed without installing or removing any other component in the array.

Abstract: A carrier for supporting an expansion card is disclosed herein. The expansion card is configured for connection to a server. The carrier includes a module that is configured to receive and removably retain the expansion card. The module is further configured to support the expansion card in a position that aligns the expansion card with a receiver in the server. The module is further configured to move with respect to the receiver to facilitate connection of the expansion card to the receiver.

Abstract: A securing device for retaining a power cord in a connected relationship with the power supply includes a substantially planar body having a first end and a second end. The first end is configured to engage the power supply. The second end is configured to engage the power cord. The body is made from a substantially rigid material.

Abstract: A clock distribution network includes: a primary clock signal and a distribution tree coupled to the primary clock signal. The distribution tree derives a plurality of separate clock signals from the primary clock signal and provides each of the plurality of separate clock signals to each of a plurality of loads. The distribution tree comprises a plurality of bow tie elements.

Abstract: An ejector mechanism for removing a computer component from a computer housing is disclosed. The computer component may be an energy storage module that includes a first electrical connector that connects the energy storage module to a second electrical connector on a back plane printed circuit board. The ejector assembly is actuated at a location remote from the energy storage module to engage the energy storage module. The ejector assembly partially ejects the module from the housing and disconnects first and second electrical connector parts.

Abstract: A two stage fully differential amplifier has been designed which works, in tandem with a TX-FIR, as a linear equalizer at low frequencies, not covered by the TX-FIR, and also acts as a linear amplifier at higher frequencies which are equalized by the TX-FIR. The amplifier as a frequency response which does not attenuate signals frequencies less than one twentieth of baud rate, creates gain peaking ion the region between one twentieth and one tenth of baud rate and maintains flat peak gain up to half of baud rate. Different aspects of the frequency response curve (such as dc gain, max gain and zero frequency) are completely programmable. Also, the differential amplifier has been designed from low power and process, voltage and temperature insensitive frequency response.

Abstract: Methods and systems for effecting cleanup and other policies for queues and similar data stores, which policies account for preferences of consumers of the data so stored. Queuing policies for local storage of one or more documents for transmission from the local storage to one or more end points for said documents are retrieved from a remote registry. Upon such retrieval, the documents are enqueued according to the queuing policies, unless, prior to such enqueuing the queues into which the documents are to be placed require creation or clean-up, for example according to one or more queue quota policies. In some cases, the documents are queued according to associated qualities of service to be accorded to delivery of said documents. Such qualities of service may be specified in the queuing policy.

Abstract: A method of performing a pre-route repeater insertion methodology for at least part of a circuit design may include: partitioning at least part of a circuit design into a plurality of tiles; determining at least one attribute of individual tiles of the plurality of tiles; and determining a repeater solution based at least in part on the determined attributes of the individual tiles. A computer implemented tool for performing a pre-route repeater insertion methodology for at least part of a circuit design may include: a module configured to partition at least part of a circuit design into a plurality of tiles; a module configured to determine at least one attribute of individual tiles of the plurality of tiles; and a module configured to determine a repeater solution based at least in part on the determined attributes of the individual tiles.

Abstract: Methods and apparatuses are presented that allow power savings on a processor executing a plurality of threads on a plurality of cores. The method may include providing a first timing signal to a processor, determining the power requirements of the processor, loading a symbol into a shift register, where the symbol may be associated with the power requirements of the processor, providing a second timing signal to the processor, where the second timing signal may include a gated representation of the first timing signal and the symbol.