Abstract: A tape drive system for a tape cartridge including a tape and wireless identification tag may read information from the wireless identification tag and write the information to the tape. The tape drive system may toggle a bit stored on the wireless identification tag to indicate that the information has been written to the tape. The information may include tape initialization information.

Abstract: A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the anonymous file by the first process, and accessing the executable file by the second process.

Abstract: One embodiment of the present invention provides a system that cancels fan noise in a computer system. During operation, the system obtains a fan noise signal using a microphone. Next, the system generates a spectral pattern based on the obtained fan noise signal. The system then uses the spectral pattern to identify a corresponding cancellation spectrum in an anti-spectra library. Next, the system generates a noise-canceling signal using the cancellation spectrum. Note that the amount of computation required to cancel fan noise is reduced because generating the noise-canceling signal using the anti-spectra library requires less computation than generating the noise-canceling signal using dynamic noise-cancellation techniques.

Abstract: A system that facilitates high-speed data transfer between integrated circuit chips. The system contains a first integrated circuit chip, which includes a capacitive receiver and an electrical-to-optical transceiver. The capacitive receiver receives a capacitively coupled voltage signal transmitted from a corresponding capacitive transmitter located on a second integrated circuit chip and converts the capacitively coupled voltage signal into an electrical signal. The electrical-to-optical transceiver converts the electrical signal to an optical signal and transmits the optical signal to an optical device through optical coupling.

Abstract: A method for dynamically allocating system resources is provided. The method initiates with identifying a goal associated with a corresponding partition of a resource being configured according to a first configuration. The method includes establishing a mathematical function yielding a value associated with the goal. Once a violation of the goal is detected due to a changing workload, alternative configurations are evaluated to meet the goal under the changing workload. Then, a highest ranked one of the alternative configurations is selected and substituted for the first configuration.

Abstract: The present invention provides a grill 10 for use in electrical equipment comprising a fan. The grill 10 comprises a substantially planar portion 90 that provides protection for (and indeed from) the blades of a fan and a handle 100 that provides means by which the grill may be held. The substantially planar portion 90 may comprise an opening 94 that facilitates stacking of a plurality of like grills 10.

Abstract: Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.

Abstract: A CAS device receives streaming media content encrypted utilizing a CAS, decrypts the received streaming media content utilizing a CAS module associated with the CAS, and transmits the unencrypted streaming media content to a rendering device. The CAS device may be operable to receive and store an additional CAS module associated with an additional CAS. The CAS device may also be operable to receive unencrypted streaming media content, encrypt the streaming media content utilizing a CAS module, and transmit the encrypted streaming media content. In another embodiment, the CAS device receives streaming media content encrypted utilizing a first CAS, decrypts the received streaming media content utilizing a first CAS module, transmits the unencrypted streaming media content from the first CAS module to a second CAS module, encrypts the unencrypted streaming media content utilizing the second CAS module, and transmits the encrypted streaming media content to a rendering device.

Abstract: A system for retrieving information from a remote server is disclosed. The system includes a browser having a webpage executing JavaScript adapted to communicate a request with client identifying information to a first server. The first server has a proxy adapted to dynamically insert information into the request received from the client and communicate the request with inserted information to a second server, whereby the request with inserted information is trusted by the second server. The second server and first server are each adapted to also provide a response to the request. A method of communicating in a networked environment is also disclosed.

Abstract: Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction to be issued.

Abstract: A method for reconstructing corrupted data, which includes determining a number of non-parity disks (n), selecting a first combination of n-1 non-parity disks, obtaining a first set of physical blocks from the first combination of n-1 non-parity disks, obtaining a parity block associated with the first set of physical blocks, reconstructing a first physical block using the first set of physical blocks and the parity block, combining the first physical block and the first set of physical blocks to obtain a first reconstructed logical block, checksuming the first reconstructed logical block to obtain a first calculated checksum, and determining whether the first calculated checksum is equal to a stored checksum associated with the first reconstructed logical block.

Abstract: A system and method for virtualizing a hardware device node for a network interface circuit or other device. In a clone driver's configuration file, multiple virtual or clone nodes are defined. Their major numbers match the major number of the driver, but a virtual node's minor number for a Style 2 driver is calculated from the hardware driver's major number and the instance or port number of the corresponding hardware node. By creating multiple clone nodes, multiple paths through the protocol stack are created. Each one can be configured differently (e.g., for different MTU sizes), and each may be assigned a different address (e.g., MAC address). The separate addresses may be registered with hardware filters to filter incoming packets at the hardware level. A traffic classifier created in the device driver manages each virtual node's association with a hardware filter.

Abstract: A method for executing transactions including obtaining a memory location required by a first transaction, where the first transaction is identified using a first transaction identification and a first transaction version; determining a second transaction with ownership of a memory group including the memory location, where the second transaction is identified using a second transaction identification and a second transaction version; copying an intermediate value associated with the memory group from the second transaction into transactional metadata associated with the first transaction; changing ownership of the memory group to the first transaction; and committing the first transaction.

Abstract: A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently. Additionally, the caching estimator process computes the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads. As a result, the caching estimator applies the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.

Abstract: One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root operations. During operation, the system performs Newton-Raphson iterations followed by a multiply for the divide or square-root operation. This result is then rounded to produce a proposed result. Next, the system performs an accuracy-check computation to determine whether rounding the result to a desired precision produces the correct result. This accuracy-check computation involves performing a single pass through a multiply-add pipeline to perform a multiply-add operation. During this single pass, a Booth encoding of an operand in a multiply portion of the multiply-add pipeline is modified, if necessary, to cause an additional term for the accuracy-check computation to be added to the result of the multiply-add operation.

Abstract: Methods and systems for defining the partitioning between operating system environments are provided. In this method, network resources, devices, and pseudo-filesystems, etc. can be partitioned. This method provides the capability to support services from native and foreign operating environments without colliding on fixed resources. This method simplifies the task of supporting multiple different operating environments. By assigning each operating environment to its own zone, multiple instances of a single operating environment or multiple different operating environments can be simultaneously supported on a single operating system kernel.

Abstract: A method involves building an intermediate form data flow graph (IFgraph) from an intermediate form data flow tree (IFtree) associated with the logic design, partitioning the IFgraph across at least three levels of granularity to obtain a partitioned IFgraph, wherein partitioning the IFgraph involves balancing a set of nodes of the IFgraph into a first subset and a second subset, wherein each of the first subset and second subset are within a predefined constraint of the cycle-based system, and wherein the balancing is performed on at least one of the levels of granularity, and rewriting the IFtree based on the partitioned IFgraph.

Abstract: A system and method for load-balancing routing of a computation within a multiprocessor system. The computation includes multiple branches of execution, not just a linear sequence of steps, and thus cannot be efficiently routed by existing minimum-delay routing schemes. The cost of a single step of the computation is calculated, possibly using a ratio of outgoing data rates from the step to the incoming data rate. That cost may then be scaled for different branches of execution of the computation leading to or from that single step. For example, the calculated cost may be multiplied by each branch's probability of being executed.

Abstract: A method and system to facilitate Peripheral Component Interconnect Express (PCIe). The PCIe may be facilitated in such as way as to limit pins consumed by a Root Complex, switch, or other chipset included on the same die a central processing unit (CPU). A slot interface card (SIC) or other devices having less expensive pins may be used to connect to and communicate with the slot.

Abstract: Methods and apparatus for processing a network connection are disclosed. The network connection is established by a first network protocol stack. A determination is made whether to offload the network connection from the first network protocol stack to the second network protocol stack. The network connection is then transferred from the first network protocol stack to the second network protocol stack when a determination has been made to offload the network connection from the first network protocol stack to the second network protocol stack. The network connection is handled by second network protocol stack until a determination has been made to offload the network connection back to the first network protocol stack. When an indicator is received indicating a request to transfer the network connection back to the first network protocol stack, the network connection is transferred back to the first network protocol stack.