Abstract: A system and method for communicating 3D branch graph data and updates to branch graph data between clients and a display server in a 3D window system. A client locally creates a branch graph. When the client ready to make the branch graph live remote, it sends the branch graph to the display server using at least one batch protocol request. The display server builds a copy of the branch graph and attaches it to a centralized scene graph that it manages. The client may subsequently induce detachment of the branch graph from the scene graph. The client may buffer up changes to the local branch graph when its remote counterpart (in the display server) is not attached to the scene graph. The buffered changes may be sent to the display server using at least one batch protocol request when the client is again ready to make the branch graph live remote.

Abstract: Techniques for processing native events associated with tasks that are concurrently supported in a virtual machine are disclosed. The techniques allow the user of a virtual machine to concurrently perform tasks even if these tasks require processing of platform-specific (or native) events (e.g., platform-specific input). A smart event-dispatcher is used to dispatch native events to multiple tasks that are concurrently supported by the virtual machine. The smart event-dispatcher can determine which one of a plurality of concurrent tasks should receive the native event for processing. The determination can be made based on a variety of different criteria. In mobile devices, the foreground task is typically the only task that is displayed for the user of mobile devices at any given time. Thus, dispatching events to the foreground task is especially useful for a virtual machine that support a mobile device.

Abstract: A 3D window system allows the contents of conventional windows created by client applications to be painted onto the surfaces of 3D objects which are then displayed in a 3D environment. The 3D window system includes a window system server and a display server. The window system server and the display server access a shared visibility structure which contains information representative of a collection of 3D objects. The window system server determines which 3D object is selected by an input event, determines a window corresponding to the 3D object, and delivers event messages to client applications which have expressed an interest in receiving events relative to the window.

Abstract: The 3D window system utilizes hardware accelerated window system rendering to eliminate the pixel copy step of 3D window system output redirection. The 3D window system includes a window server that directs the window system device driver graphics routines to render into the texture memory of a graphics device.

Abstract: Various embodiments of systems and methods of providing heightened data integrity in a data processing system are disclosed. A data processing system may include a host computer system, an interconnect coupled to the host computer system, and a storage array coupled to the interconnect and configured to store data received from the host computer system over the interconnect. A data integrity device including at least one processor may be coupled to the interconnect. The data integrity device is configured to be enabled and disabled. If the data integrity device is disabled, the data processing system may provide a base level of error protection for the data. If the data integrity device is enabled, the processor is configured to perform a first data integrity operation on the data in order to provide a heightened level of error protection for the data.

Abstract: A computer program embodied on a computer readable medium is provided for combinatorial test generation. The computer program includes a code segment that obtains an assertion, wherein the assertion includes a plurality of assertion variables, and a code segment that generates a slot tree having a plurality of nodes, wherein the slot tree represents the assertion variables of the obtained assertion. Further included is a code segment that processes the nodes of the slot tree to generate tests for the assertion. As above, the slot tree can comprise a plurality of leaf slot nodes that represent the actual assertion variables, each leaf slot node including a value set for the assertion variable that the leaf slot node represents. The slot tree can also include a plurality of non-leaf slot nodes that are capable of referencing other nodes, wherein the other nodes can be leaf slot nodes and non-leaf slot nodes.

Abstract: A system is provided that facilitates placing repeating flip-flop stations on signal lines within an integrated circuit. The system operates by first receiving a layout that includes multiple functional blocks, and a netlist that specifies interconnections for signals between these functional blocks. The system determines a transit time for a signal interconnecting the functional blocks. If this transit time exceeds an allowed time, the system divides the interconnection into two or more sections, wherein the transit times on the sections are each less than the allowed time. The system then places a repeating flip-flop station within a channel on the integrated circuit in a position that allows the transit time on these sections to be met. Next, the system routes the signal from the originating functional block through a flip-flop located at the repeating flip-flop station to a receiver at the destination functional block.

Abstract: A computer system includes a cache memory a functional unit in communication with the cache memory, and a reconfiguration module. The functional unit executes applications using the cache memory. The reconfiguration module is for determining an optimal configuration of cache memory for a particular application and programming the cache memory to the optimal configuration. A method of reconfiguring cache memory includes determining an optimal configuration of cache memory for a particular application executed by a functional unit using a cache memory and programming the cache memory to the optimal configuration.

Abstract: A mechanism for the migration of open network connections is described herein. According to one or more embodiments of the present invention, an active computing environment called compute capsule is provided. Each capsule has a unique locator. Packets are used to send information between capsules using the locators. When a capsule migrates, any open network connections that existed before the migration may continue when the capsule finishes the migration.

Abstract: The disclosed system is directed towards a multi-hinge. The multi-hinge comprises a body including a first end and a second end opposite the first end. The first end defines a beam axis of rotation and the second end defines a bracket axis of rotation. A bracket coupling is rotatably coupled to the second end of the body along the bracket axis of rotation. The bracket coupling includes a rotary section rotatably coupled to the second end of the body along the bracket axis and a mounting section disposed coaxially with and rotatably coupled to the rotary section. The multi-hinge includes a base rotatably coupled to the first end of the body about the beam axis of rotation. The multi-hinge further includes a moment arm pivotally coupled to the base at a radial distance from the beam axis and pivotally coupled to the rotary section of the bracket coupling at the radial distance from the bracket axis. The multi-hinge includes a torsional preloading member coupled between the body and the base.

Abstract: One embodiment of the present invention provides a system that facilitates accelerated Soft-Error Rate (SER) testing of circuitry. The system starts by collecting a radioactive gas from the atmosphere and concentrating the radioactive gas in a testing chamber. Once the desired amount of radioactive gas is present in the testing chamber, the system SER tests the circuitry in the testing chamber by bombarding the circuitry with particles emitted from the radioactive gas while running testing procedures.

Abstract: An apparatus includes a computing node and a metadata server. The computing node may transmit a request to open a file to the metadata server, which may provide a corresponding file identifier to the computing node. The computing node may use the file identifier to directly access the storage storing the file. In one embodiment, the storage may be an object-based storage. The storage may receive the file identifier with an access command and may perform the mapping from file identifier to storage blocks internally. Thus, accesses to the storage may be performed on an arbitrary boundary within the file. In other words, the entire block including the data needed by the computing node may not be transferred to the computing node. Instead, the storage may select the data requested from the file (e.g. via an offset and a number of bytes or some similar mechanism) and return that data to the computing node.

Abstract: A dedicated service finder runs on each host on which data management services run. This service finder caches handles that allow clients to manage the corresponding service and keeps track of other hosts that are also running the service finder. In one embodiment, the service finder registers itself with an existing lookup service so that a client can perform a single lookup for the service finder and then obtain other services from it. Accordingly, only a single lookup is required to obtain all the services running on a specific host. In accordance with another embodiment, the service finder monitors events generated by existing lookup services that occur when other service finders register with the lookup services. In this manner, the service finder can maintain a list of other hosts that have service finders running on them. This arrangement allows a client that has located one service finder to retrieve from that service finder information concerning other hosts and data services running on those hosts.

Abstract: This invention is an apparatus, method, and system for translational lookaside buffer coherency in computer systems having a plurality of processors, each having an associated TLB for storing address translation data, and the computer system having a plurality of independent paths upon which the plurality of processors are distributed and a TLB message transmitted on said plurality of independent paths.

Abstract: Embodiments of the invention comprise techniques to detect support for a given input device by a screen element of a graphical user interface (GUI). In one embodiment of the invention, a runtime version of a screen element's program code is examined to detect an ability to process a device's events. In another embodiment of the invention, a determination is made at runtime whether a screen element delegated processing of a given input device's events to other program code. In yet another embodiment of the invention, the runtime version of a screen element's program code is examined to detect a declaration of program code that is indicative of a the screen element's support or non-support of a given input device. In yet another embodiment of the invention, one or more of the previously-identified embodiments can be combined.

Abstract: A method is provided that enables native code, dynamically compiled from platform-independent code by one task of a multitasking virtual machine, to be used by other tasks. The system interprets the platform-independent code of a method for a threshold number of interpretations, and then produces class initialization dependent (CID) native code. The runtime of the system guarantees that a task uses CID code of a method only when all of the classes of an initialized set associated with the CID code have been initialized by the task, and otherwise, interprets the platform-independent code of the method. This allows the compiler to avoid generating class initialization barriers for classes from the initialized set. After a threshold number of failures to execute the CID code of a method, task re-entrant code is generated to replace the interpretation of its platform-independent code.

Abstract: One embodiment of the present invention provides a system that facilitates relocating an object in a computer system that provides an object-addressed memory hierarchy. During operation, the system receives a new address specifying to where the object is to be relocated in main memory. The system then retrieves an object table entry associated with the object. This object table entry contains a current address for the object, which is used to translate an object identifier for the object into a corresponding physical address for the object in main memory. Next, the system clears an evicted indicator from the object table entry, wherein the evicted indicator is set whenever the object is modified in main memory. The system then copies the object from the current address to the new address. After copying is complete, the system performs an atomic operation that swaps the current address in the object table entry with the new address if the evicted indicator remains clear.

Abstract: A system and method for superimposing a sequence number of a packet into the CRC segment of the packet thereby allowing more bandwidth in the payload portion of the packet for carrying data is described. Also described is a method of acquiring additional information on the type of error in a packet, e.g., data transmission errors or sequence errors, from analyzing a CRC error. For example, a reported CRC error can be the result of the receipt of a packet with a sequence number the receiver is not expecting (which is a normal occurrence on transmission links due to transmitters resending packets that a receiver has already accepted) or can result from a real error in the transmission of a packet. A first error code check (CRC) value is calculated for the payload segment of a data packet. A second CRC value is calculated for the sequence number of the data packet. The first CRC value and the second CRC value are combined thereby creating a third CRC value.

Abstract: A circuit topology for high-speed memory access. In one embodiment, an electronic circuit includes a memory controller. The memory controller is coupled to a memory module by a first plurality of transmission lines. The memory module may include a second plurality of transmission lines coupled to the first plurality. The memory module further includes a first memory bank coupled to the second plurality of transmission lines and a third plurality of transmission lines. A second memory bank may be coupled to the third plurality of transmission lines. Each of the first, second, and third pluralities of transmission lines may be part of a common bus.

Abstract: The present invention is a method and apparatus for a reliable boot device. The invention comprises a plurality of disk drive which appear to be the same logical unit (LUN) to the computer. Any disk can serve as the boot drive, and any remaining disk serves as a backup boot drive. The LUN is mirrored, which means information written to any disk is automatically written to all disks. In the event of failure of one of the disks, the invention automatically indicates that one disk has led and switches to using all disks which have not failed. A technician can remove the failed disk and replace it with a new disk while the invention is still in use without interruption in the usability of the computer. Once the new disk is placed in the invention, the information on the remaining disks is automatically mirrored to the replacement disk.