Abstract: A system and method provides dynamic and static type support for multiple definitions of individual types in a distributed object environment. Fully scoped object names incorporating prefixes are used to distinguish objects. The fully scoped names are used for both dynamic type determination through an interface repository and for statically compiled types in client and server stub routines. In the interface repository, a prefix naming context is provided for each root interface definition language context, allowing multiple definitions for objects with the same interface definition language object name, where each such definition resides in a separate prefix naming context. In one embodiment, the prefix naming contexts are defined by prefix interface definition objects. In another embodiment, the fully scoped object names are embedded by an interface definition language compiler in stub and skeleton code routines. RRS.

Abstract: Methods and apparatus for providing a progress associated with an executing process are disclosed. A progress report is generated in a progress reporting language, the progress reporting language indicating a progress of one or more steps in the executing process. The progress report is then provided to a user interface mechanism capable of interpreting the progress reporting language, where the user interface mechanism is adapted for generating a user interface indicating the progress of the one or more steps in the executing process. The user interface mechanism receives the progress report, ascertains the progress of the steps in the executing process from the progress report, and generates a user interface indicating the progress of the steps in the executing process.

Abstract: A mother board retaining bracket is mounted to an outer circuit board housing and supports an edge of a mother board. The mother board retaining bracket prevents the mother board from moving, e.g., during transportation, and prevents the associated failure of the computer system. The computer system further includes single and double locker belt retaining brackets. The single locker belt retaining bracket extends across a retaining clip on one side of a circuit board and locks the retaining clip in place. The double locker belt retaining bracket extends across retaining clips on both sides of a circuit board and locks the retaining clips in place. In this manner, the single and double locker belt retaining brackets prevent the retaining clips from becoming shook loose.

Abstract: A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may generate a plurality of memory requests each including address information and corresponding error detection information. The corresponding error detection information is dependent upon said address information. The memory module may receive each of the plurality of memory requests. An error detection circuit within the memory module may detect an error the address information based upon the corresponding error detection information and may provide an error indication in response to detecting the error.

Abstract: Provided is a method, system, and program for encrypting files in a computer in communication with a volatile memory and non-volatile storage device. An encryption code is generated to encrypt a file and a decryption code is generated to decrypt one file encrypted with the encryption code. The decryption code is loaded into the volatile memory, wherein the decryption code is erased from the volatile memory when the computer reboots. Files written to the non-volatile storage device are encrypted using the encryption code and the decryption code in the non-volatile memory is used to decrypt files encrypted with the encryption code to transfer from the non-volatile storage device to the volatile memory.

Abstract: An apparatus and method for locating free data blocks in a microprocessor-based system for which snapshots are maintained. The snapshots are stored periodically, but only a subset of live snapshots is retained in order to reduce the total amount of storage needed for the snapshot information, such that their snapshot numbers are not sequential and there are gaps in the snapshot times. For each data block to be accessed, an allocation time and a deallocation time are stored in an allocation table. When a data block is needed, its allocation and deallocation times are compared with the live snapshot times to determine whether that data block is available. If not, the system iterates through the other data block allocation information until a free data block is located. If so, the system writes to that data block, and repeats the procedure as necessary to locate additional free data blocks.

Abstract: A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system. Alternatively, if the memory access rate has been exceeded, then the access is delayed until the current time interval has expired and a subsequent time interval is started as the current time interval and the access is applied to the memory system.

Abstract: A mechanism for enabling session information to be shared across multiple processes in a multi-process environment is disclosed. There is provided a shared persistent memory-mapped file in a file system, which is mapped to the memory space of each of the processes. This file is used by all of the processes to store session information. Because the memory space of each process is mapped to the shared file, each process is able to access and manipulate all of the sessions in the system. Thus, sessions are no longer maintained on a process-specific basis. Rather, they are maintained on a centralized, shared basis. As a result, different requests pertaining to the same session may be serviced by different server processes without any adverse effects. Each process will be able to access and manipulate all of the state information pertaining to that session. By enabling session information to be shared, this mechanism eliminates the session management errors experienced by the prior art.

Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

Abstract: A system and method for determining the desired decoupling components for a power distribution system having a voltage regulator module. The system may employ a mathematical model of a voltage regulator circuit, such as a switching voltage regulator. The mathematical model may be a SPICE model, or a circuit model in another format. The method may include simulating the operation of the power distribution system to obtain a estimate of the bulk capacitance required for effective decoupling. For digital systems, the method may include a cycle-by-cycle simulation of the power distribution system, wherein the simulation occurs over a number of clock cycles. The performance of the power distribution system may then be analyzed for each simulated clock cycle. The simulation may also include analyzing the transient responses and loop stability of the power distribution.

Abstract: A controller and method are provided for monitoring and controlling a temperature of an integrated circuit to inhibit damage from a thermal problem. The controller and method allow for individual temperature thresholds for each of one or more temperature sensors. Digital filtering of values received from temperature sensors is also provided. A variety of actions can be selected for execution upon a determination of an over-temperature condition of the integrated circuit, including assert an over-temperature pin, assert an over-temperature bit in an error register of said controller, assert an over-temperature bit in an error register of said microprocessor, issue an over-temperature interrupt to a service bus of said integrated circuit, cause a trap, slow an operating frequency of said integrated circuit, stop said integrated circuit, and do nothing.

Abstract: Methods and systems consistent with the present invention provide a Supernet, a private network constructed out of components from a public-network infrastructure. The Supernet provides channel-specific file system views such that the file system of the Supernet is partitioned on a per-channel basis so that nodes on one channel see a different view of the network file system than the nodes on a different channel.

Abstract: A single field replaceable storage or computer system may include a processor coupled to a peripheral bus by a bridge device. The field replaceable unit (FRU) may also include system memory coupled to the processor and a network interface coupled to the peripheral bus. One or more drive controllers may also be included coupled to the peripheral bus. Additionally, the single field replaceable unit includes an array of disk drives coupled to the one or more drive controllers. The array of disk drives may be configured as one or more RAID logical volumes and exported or presented to client machines as one or more file systems through the network interface. The processor, system memory, network interface, drive controllers, and array of disk drives are all packaged together as a single field replaceable unit. The processor, system memory, network interface, drive controllers, and array of disk drives may be configured not to be individually field serviceable or replaceable.

Abstract: A system for servicing communication queues may include memory configured to store a hierarchical channel map having a plurality of levels wherein each bit of the lowest level is mapped to a different one of a plurality of communication channels and wherein each bit of each higher level is mapped to a group of bits at the next lower level. The system may include a host adapter configured to maintain the hierarchical bitmap wherein each bit at the lowest level is set if the channel to which it is mapped has a pending communication request and is cleared if not. Each bit of each higher level is set if at least one bit is set in the lower level group to which is mapped and cleared if not. The host adapter may be configured to examine the hierarchical bitmap in order to determine a next one of the communication channels to service. At each level of the hierarchical channel map a service mask may be provided to track which bits have already been traversed at that level.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.

Abstract: A stub retrieval and loading subsystem is disclosed for use in connection with a remote method invocation system. The stub retrieval and loading subsystem controls the retrieval and loading of a stub for a remote method, into an execution environment, to facilitate invocation of the remote method by a program executing in the execution environment. The stub retrieval subsystem includes a stub retriever for initiating a retrieval of the stub and stub loader for, when the stub is received by the stub retriever, loading the stub into the execution environment, thereby to make the stub available for use in remote invocation of the remote method. In one embodiment, the stub retrieval and loading subsystem effects the retrieval and loading for a program operating in one address space provided by one computer, of stub class instances to effect the remote invocation of methods which are provided by objects operating in another address space, which may be provided by the same computer or a different computer.

Abstract: A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

Abstract: A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static fields are extracted from the original classes. A separate copy of the static fields is created for each of the utilizing applications. A static field class which includes instance fields corresponding to the static fields may be created, wherein each instance of the static field class corresponds to one of the utilizing applications. Access methods for the one or more static fields may be created, wherein the access methods are operable to access the corresponding separate copy of the static fields based upon the identity of the utilizing application. A single access methods class may be created for each original class, wherein the single access methods class includes the access methods for accessing the extracted fields from the original class.

Abstract: Techniques for providing application services in a multi-CPU environment are disclosed. The techniques provide a “vertical perimeter” framework suitable for processing applications and their related data in multi-CPU environments. In this vertical perimeter framework, an instance (i.e., a copy) of a service provider application is provided for each CPU in the multi-CPU environment in accordance with one embodiment of the invention. Each one of the application instances is processed by a CPU that is designated to process that particular application instance. Furthermore, each one of the CPU's is assigned to process incoming connections from a particular network interface.

Abstract: One embodiment of the present invention provides a system that reduces the time required to access registers from a register file within a processor. During operation, the system receives an instruction to be executed, wherein the instruction identifies at least one operand to be accessed from the register file. Next, the system looks up the operands in a register pane, wherein the register pane is smaller and faster than the register file and contains copies of a subset of registers from the register file. If the lookup is successful, the system retrieves the operands from the register pane to execute the instruction. Otherwise, if the lookup is not successful, the system retrieves the operands from the register file, and stores the operands into the register pane. This triggers the system to reissue the instruction to be executed again, so that the re-issued instruction retrieves the operands from the register pane.