Abstract: A method for executing an instruction stream includes partitioning the instruction stream using a partition point to obtain a first partition of the instruction stream and a second partition of the instruction stream, configuring the first partition and the second partition to fit separate e-caches, analyzing the first partition and the second partition to generate a runtime execution facility and a data transfer facility, and executing the first partition and the second partition on separate processors using the runtime execution facility and the data transfer facility.

Abstract: A system and method for managing persistent objects with a persistent object framework is disclosed. The persistent object framework receives queries and instructions from an application for data from the persistent objects. The persistent objects are stored in data sources, such as databases or repositories. The persistent object framework may create, save, update, access, search, and delete persistent objects. Further, the persistent object framework caches applicable persistent objects for the application. The persistent object framework provides the caching for the persistent objects. The persistent object framework supports both Lightweight Directory Access Protocol and relational databases.

Abstract: Techniques for providing security context and firewalls in computing environments are disclosed. The security context includes cryptographic operations that can further enhance security. A security context block that includes a security context identification (ID) and a cryptographic system is disclosed. The security context identification (ID) can be provided for and assigned to various components of the computing system as means for security identification. Using the cryptographic system, various cryptographic operations can be performed on the security context identification (ID) to further enhance security. For example, security identifiers can be authenticated before it is presented to a firewall. After, successful authentication, the firewall can be used to determine whether the security identifier identifies an associate with access privileges.

Abstract: A lock management technique that combines low-space overhead via sharing of lock states of equal value with comprehensive support for bulk delegation of locks has been developed. Operating in conjunction with methods for validating delegation requests prior to their execution, bulk delegation of locks can be achieved with computational costs that are generally independent of the number of lock being delegated. This property, added to the low-space overhead representation of locks via lock state sharing, offer a combination that may be particularly attractive for systems that demand for fine-granularity locking, large transaction sizes (in term of number of locks acquired) and efficient bulk delegation mechanisms.

Abstract: Methods and systems consistent with this invention conserve computer resources in a hierarchical memory system by preventing scratch data from unnecessarily being copied from a lower hierarchy to a higher hierarchy storage space. Such methods and systems invalidate portions of data in the higher hierarchy storage space so that the coherence protocol does not copy the data to the lower hierarchy storage space. For example, methods and systems consistent with this invention hierarchically store data in a computer system having a main memory and a cache memory. Such methods and systems designate an area of the cache memory that contains scratch data as invalid, wherein the invalid data occupies less space than a maximum space of the cache memory, and permit a writing over of the invalid data in the cache memory.

Abstract: A count down monitor may be configured to automatically generate an alert that one or more limited lifetime components included in multiple computer systems are due for replacement. For example, a system and method that provides up-to-date system configuration data for the multiple computer systems may include and/or interact with one embodiment of a count down monitor. The count down monitor may be configured to automatically generate an alert to indicate one or more of the limited lifetime components are due for replacement. The alert may be visual. The count down monitor may be configured to generate various types of alerts.

Abstract: Apparatus, methods, and computer program products are disclosed for a process of terminating a thread in a clean, certain, and forcible manner. A thread is forcibly terminated in such a manner that data structures in the system are not left in an inconsistent state and the overall system status is not damaged. The methods and systems described are for terminating a thread in a computer language execution environment. Methods are implemented in an interpretive loop executing in a language that is interpreted and in runtime support libraries in a language that are not interpreted. A method of forcibly terminating a thread in a computer language execution environment is described. A thread receives a terminate thread command. The thread has associated with it a termination flag, a value of the termination flag being immutable once set, and one or more monitors. The termination flag is then set for the thread.

Abstract: A method and apparatus for regulating resonance in a computer system I/O interface is provided. A shunting impedance/resistance is arranged across a power supply of the I/O interface. The shunting impedance/resistance is controlled by circuitry that is arranged to detect voltage overshoot conditions in the I/O interface. The circuitry has (1) an analog front end that is arranged to detect power supply oscillations relative to a grounded terminal, (2) an amplifier (or logic conversion circuit) that is arranged to convert an output signal from the analog front end to a digital signal, and (3) a shunting apparatus arranged to modify power supply behavior in the I/O interface dependent on the digital signal.

Abstract: A method for optimizing buffers in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting buffers at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting buffers at particular nodes to address timing violations are within the integrated circuit design.

Abstract: Systems and methods for increasing the execution speed of virtual machine instructions for a function are provided. A portion of the virtual machine instructions of the function are compiled into native machine instructions so that the function includes both virtual and native machine instructions. Execution of the native machine instructions may be accomplished by overwriting a virtual machine instruction of the function with a virtual machine instruction that specifies execution of the native machine instructions. Additionally, the original virtual machine instruction may be stored so that the original virtual machine instructions can be regenerated.

Abstract: Embodiments of a routing system are disclosed, including a method for routing communications in a storage system. The storage system may include multiple nodes interconnected by an interconnection fabric that provides multiple independent paths between a source node and a destination node. Some nodes may be connected to one or more disk drives. The method may include receiving a communication to be sent from a source node to a destination node, selecting a communication path from the multiple independent paths, and sending the communication on the selected communication path. This process may be repeated so that multiple communications may be sent. Each communication path may be selected according to a preference assigned to it, so that a more preferred path is selected more often than a less preferred path. The preferences may be updated to reflect changed conditions in the interconnection fabric.

Abstract: A method and apparatus for providing an EMI seal in a system chassis. The EMI seal is provided by a bezel assembly for a storage medium drive. The bezel assembly includes a front bezel having an aperture through which a tray can extend for loading and unloading of the storage medium drive, and a tray bezel attached to the tray. Attached to the front bezel is an electrically conductive link. Both the front bezel and the tray bezel include an electrically conductive inner surface. Upon closing the tray, the electrically conductive link provides an electrical connection between the inner surface front bezel and the inner surface of the tray bezel.

Abstract: A multiprocessor, multi-program, stop-the-world garbage collection program is described. The system initially over partitions the root sources, and then iteratively employs static and dynamic work balancing. Garbage collection threads compete dynamically for the initial partitions. Work stealing double-ended queues, where contention is reduced, are described to provide dynamic load balancing among the threads. Contention is resolved by using atomic instructions. The heap is broken into a young and an old generation where parallel semi-space copying is used to collect the young generation and parallel mark-compacting the old generation. Speed and efficiency of collection is enhanced by use of card tables and linking objects, and overflow conditions are efficiently handled by linking using class pointers. A garbage collection termination employs a global status word.

Abstract: A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense amplifier is monitored and the amplification control parameter to the sense amplifier is adjusted according to the temperature of the sense amplifier.

Abstract: A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.

Abstract: A high-speed domino logic with improved cascode keeper circuit uses an inverter delay element and an additional transistor to introduce a transition delay time and node isolation time to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of high-speed domino logic with improved cascode keeper circuit. The high-speed domino logic with improved cascode keeper circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only a minimum of one new inverter and one new are required, the modification of the invention is space efficient and readily incorporated into existing designs.

Abstract: A method and apparatus for predicting load addresses and identifying new threads of instructions for execution in a multithreaded processor. A load prediction unit scans an instruction window for load instructions. A load prediction table is searched for an entry corresponding to a detected load instruction. If an entry is found in the table, a load address prediction is made for the load instruction and conveyed to the data cache. If the load address misses in the cache, the data is prefetched. Subsequently, if it is determined that the load prediction was incorrect, a miss counter in the corresponding entry in the load prediction table is incremented. If on a subsequent detection of the load instruction, the miss counter has reached a threshold, the load instruction is predicted to miss. In response to the predicted miss, a new thread of instructions is identified for execution.

Abstract: A method for determining display element attribute values from an object represented by the display element includes defining a display element view including at least one elementary view that is capable of determining a display element attribute value, receiving a display element attribute value request, determining the first view for the display element and ascertaining at least one display element attribute value for the display element based upon the first view. An apparatus for determining display element attribute values from an object represented by the display element includes a definer to define a display element view including at least one elementary view that is capable of determining a display element attribute value, a receiver to receive a display element attribute value request, a determiner to determine the first view for the display element and an ascertainer to ascertain at least one display element attribute value for the display element based upon the first view.

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using a global data structure.

Abstract: One embodiment of the present invention provides a system that facilitates atomically updating selected bits within a register in a computing system. During operation, the system receives a command to update selected bits within the register. This command includes a data word and a control bit pattern. Next, the system examines the control bit pattern to determine an operation to be performed on the register. The system then performs the operation, which involves using the dataword to modify a content of the register atomically, without blocking subsequent commands to update the register.