Abstract: Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node.

Abstract: A mechanism is provided for enabling a request to be evaluated prior to the request being disposed. Particularly, an evaluation function is associated with a thread pool. Whenever a thread is to be assigned from that thread pool, the evaluation function may be invoked. The evaluation function may be invoked in response to one or more conditions being satisfied, or it may be invoked each time a thread is needed from that thread pool. When invoked, the evaluation function performs an evaluation on the request. Based upon the evaluation, the evaluation function may take one or more actions. For example, if the evaluation function determines that the request is a high priority request, then it may ensure that the request will be processed regardless of system workload. The evaluation function is user specifiable; thus, it may be programmed to perform any desired operations, and to take any desired considerations and factors into account.

Abstract: The present invention provides a method for devices to be remotely accessed over a network. A remote device drive is coupled to a bus device driver at a network client. The remote device driver communicates to a remote bus proxy to a driver service in the server domain. A device manager provides responsibility for discovering services on network clients, enabling driver services to use the devices, notifying other driver services of the availability of devices, notifying clients of the permission to use a device by a service, and tracking connected devices.

Abstract: A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.

Abstract: An expansion enclosure allows additional expansion cards to be used with a computer system. The enclosure exhibits a small footprint (e.g., one rack unit, or 1¾ inches) for installation in a rack or other area in which space is limited. The enclosure accepts one or more (e.g., four) expansion cards, which are connected to a removable expansion card cage. The removable cage forms part of the structure of the enclosure and provides strength and rigidity. A stabilizer may be removably but securely installed in the enclosure to stabilize or hold the removable cage as a card is installed in or removed from the cage.

Abstract: One embodiment of the present invention provides a system for finding the roots of a polynomial or a quadratic equation with interval coefficients. The system operates by receiving a representation of a polynomial equation, which can be a quadratic equation of the form F(x)=Ax2+Bx+C=0, wherein A=[AL, AU], B=[BL, BU] and C=[CL, CU] are interval coefficients. Next, the system computes intervals containing roots of the functions F1(x), F2(x), F3(x) and F4(x), wherein F1(x)=ALx2+BLx+CL, F2(x)=AUx2+BUx+CU, F3(x)=ALx2+BUx+CL and F4(x)=AUx2+BLx+CU. The system then places the computed intervals into a list, L, and orders the computed intervals in L by their left endpoints, so that for a each entry, Si=[SiL, SiU], SiL?Si+1,L. Next, the system establishes interval roots for F(x) from the interval entries in list L.

Abstract: A dithering system comprising a dithering unit, a storage medium, and an averaging unit. The dithering unit is configured to receive a set of data values, to add dither values to the data values, and to truncate the resultant addition values to L-bit truncated values. The storage medium is configured to store the L-bit truncated values. The averaging unit is configured to read the L-bit truncated values from the storage medium, and to compute an average value using at least a subset of the L-bit truncated values. The dither values may have an average value of approximately one-half. The dither values may approximate a uniform distribution of numbers between ?A+½ and A+½, wherein A is greater than or equal to one. Alternatively, the dithering unit may receive a temporal stream of data values, and the average unit may perform a temporal average (e.g. an FIR filter). The dithering system may be incorporated in a graphics system. In this case, data values may represent rendered sample values (e.g.

Abstract: One embodiment of the present invention provides a system that automatically computes a derivative of a numerical expression within a digital computer system. The system operates by receiving a representation of the numerical expression, wherein the numerical expression includes one or more independent variables. Next, the system forms an expression tree for the derivative of the numerical expression with respect to an independent variable, wherein the expression tree makes use of temporary variables to form results of sub-expressions for computing the derivative. While forming this expression tree, the system seeks to introduce only temporary variables and associated sub-expressions as necessary to eliminate repeated common sub-expressions, thereby substantially minimizing the number of temporary variables. The system subsequently uses this expression tree to compute the derivative of the numerical expression during a computation.

Abstract: In a Pure Fill Via Area (PFVA) extraction design flow, the extracted PFVAs may violate the minimum via spacing rule with the existing vias and may also violate the minimum via spacing rule among themselves. Such extracted PFVA violations may be corrected in an automatable design flow not requiring user intervention by removing any portion of a PFVA falling within a minimum via spacing rule of an existing via, to form a DRC-clean PFVA relative to existing vias, and removing any portion of a DRC-clean PFVA falling within the minimum via spacing rule of another DRC-clean PFVA.

Abstract: An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Abstract: A method and apparatus of performing active update notification. Components of an application are able to specify interest in a data object or set of data objects by registering an interest object with an update management component of the application. The interest object specifies the interested application component, as well as the identity of one or more data objects or an attribute value or range of values to associate with data objects. When modifications are made to data objects corresponding to the registered interest objects, the interested application component or components receive an update notification from the update management component. In one embodiment, active update notification is performed within a multi-tier application. An update management component exists at the application server on the application tier, as well as at each client in the client tier.

Abstract: An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.

Abstract: The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.

Abstract: A method for modeling the power behavior of a pipelined processor has been developed. The method uses a power model integrated into a cycle accurate simulator. To create the power model, design blocks of the processor are divided into sub-blocks. Power modeling equations for each sub-block are developed by collaboration between the sub-block circuit designer and the simulator developer, using activity information relevant to the sub-block that is available in the simulator model. Each equation is calculated multiple times with different sets of power parameters to represent varying power conditions. Every simulation cycle, sub-block power is summed to generate full-chip power for multiple power conditions.

Abstract: A method for reducing a transistor circuit netlist for clock network timing verification is provided. Further, a simulation tool that reduces a transistor circuit netlist such that nonlinear circuit properties are preserved is provided. Further, a computer system that improves clock network performance by simulating a netlist that is generated from a reduced transistor circuit netlist is provided.

Abstract: A thermal control apparatus using heat pipes. The thermal control apparatus includes a heat pipe having a hollow interior at least partially filled with a vaporizable liquid. The heat pipe further includes a threaded outer surface configured for coupling the heat pipe into an aperture having a threaded inner surface. The threaded outer surface maybe an integral portion of the heat pipe, or may be implemented using a separate piece that coupled to the heat pipe. A thermal control apparatus using the heat pipes may be implemented with a heat spreader having one or more apertures, wherein each of the apertures includes a threaded inner surface. A heat pipe having a threaded outer surface may be positioned in one of the apertures. The thermal control apparatus may be mounted on a printed circuit board in the proximity of one or more electronic components.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: An electrical connector for conveying signals between two circuit boards includes a first connector portion including a first array of board contacts for connection to a first corresponding footprint on a first circuit board. The connector also includes a second connector portion including a second array of board contacts for connection to a second corresponding footprint on a second circuit board. The signals include a plurality of signal groups each including a different plurality of related signals. Each of the signal groups is assigned to a grouping of related board contacts of the first array and to a corresponding grouping of related board contacts of the second array. When the first connector portion and the second connector portion are mated, each grouping of board contacts of the first array is electrically coupled to the corresponding grouping of board contacts in a transposed location in the second array.

Abstract: A system and method for hot swapping daughtercards in high availability computer systems. In one embodiment, a high availability computer system includes a peripheral bus. Daughtercards may be added to the computer system by inserting them into connectors associated with the peripheral bus. The daughtercards are configured to allow their insertion or removal from the computer system without interruption to system operations. When inserted into a computer system, a daughtercard may be powered up by power control circuitry on the daughtercard. When the daughtercard is powered up, it may then assert a configuration change signal. The computer system may then respond to the assertion of the configuration change signal by establishing software communications with the daughtercard. The configuration change signal may be driven to a storage unit located within a bus interface unit of the computer system. The state of the configuration change signal may be stored within a storage location of the storage unit.

Abstract: The present invention provides a method and apparatus for desirable network components. One embodiment selects connection components for use in network components, where the most desirable components are selected from a set of components associated with a plurality of network protocols having identical physical layers. Another embodiment of the present invention uses Gigabit Ethernet connection components, which communicate using the Fiber Channel network protocol. Since the physical layer of Gigabit Ethernet and Fiber Channel are the same, the less expensive Gigabit Ethernet components carry the electronic signals to the Fiber Channel devices in the same way as Fiber Channel connection components. Thus the embodiment communicates using the Fiber Channel protocol over Gigabit Ethernet components. In yet another embodiment of the present invention, the network component is a storage device such as a redundant array of inexpensive disks (RAID) device.