Abstract: A system for managing cables is disclosed herein. A preferred aspect of the system comprises a flat panel monitor having a front surface, a rear surface, a left side surface and a right side surface. The system also comprises a plurality of downwardly facing cable portals coupled to the rear surface of the flat panel monitor and a stand coupled to the rear surface of the flat panel monitor, wherein the flat panel monitor is forwardly rotatable on said the on a horizontal axis; and a plurality of releasably connectable retaining member are coupled to the rear surface of the flat panel monitor.

Abstract: A data imaging system is managed by a three-tiered system. The lowest, or agent, tier comprises Common Information Model (CIM) provider objects that reside in the host providing the data imaging service and can make method calls on low-level kernel routines that implement the service. The middle, or logic, tier is a set of federated Java beans that communicate with each other, with the CIM providers and with the upper tier of the system and provide the business logic for the system. The upper, or presentation, tier of the inventive system comprises web-based presentation programs that can be directly manipulated by management personnel to view and control the system from virtually anywhere in the network.

Abstract: Methods and apparatus are presented for presenting information on a display. In one aspect, information may be presented on a display after power up, and prior to the display being placed in a sleep mode. Additionally, the disclosure provides for detecting whether video has been applied to the display, and displaying a corresponding error message in no applied video has been detected. The disclosure further provides for determining whether a video error exists with the applied video, and displaying a corresponding error message if a video error is detected.

Abstract: According to an embodiment of the present invention, a method and apparatus is described for selecting dependencies between a fast scoreboard and a slow scoreboard in an out of order processor. The processor fetches instructions in groups eight instructions. Each group of eight instructions is mod-eight rotated. The instructions in the scoreboards are configured into multiple octets. A select mask for the first instruction of each octet is generated using a predefined truth table. The select masks for remaining instructions in the octets are generated using the first mask. The write pointer for the current instruction is used to select the masks for the group of eight instructions. The selected masks are then used to multiplex dependencies between the scoreboards. The selected masks are configured to multiplex dependencies between the scoreboards for single or multi-strand operations.

Abstract: A system and method for adding routing information for a node to a routing table, which efficiently makes necessary changes to the routing table to support routing to and from the node, while maintaining the deadlock-free quality of the paths described by the routing table. The routing table is generated by storing routing information in the routing table that reflects and describes a deadlock-free set of paths through a network of nodes. A row of entries is added to the routing table describing how to forward data units from the node. A column of entries is added to the routing table describing how to forward data units addressed to the node. The forwarding information within each entry added to the routing table maintains the deadlock-free quality of the set of paths represented by the forwarding table.

Abstract: A method, computer program, signal transmission and apparatus pre-verify instructions in a module of a computer program one module-at-a-time. First it is determined whether checking an instruction in a first module which is loaded requires information in a referenced module different than the first module. If the information is required, a constraint for the referenced module is written without loading or otherwise accessing the referenced module. During linking it is determined whether a first module which is loaded has passed pre-verification one-module-at-a-time before linking. A pre-verification constraint on a constrained module is read, if any, if the first module has passed such verification. If any pre-verification constraint is read, the pre-verification constraint is enforced if the constrained module is already loaded.

Abstract: A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing computer system is allocated to each node, called local memory space. Two logical address spaces are mapped to the local memory of each node. A coherent memory replication (CMR) address space stores shadow pages of data from remote nodes and a local address space stores local data. A bit within a local physical address identifies whether data is a shadow page, which is stored in CMR space, or local data, which is stored in local address space. When a transaction requiring a coherency operation is performed, the CMR bit indicates whether a local physical address to global address translation is required. In one embodiment, if the CMR bit is clear, the local physical address is the same as the global address and the local physical address is used for the coherency operation.

Abstract: The present invention provides a means to support new and modified platforms without the need to modify the system software kernel. The invention uses an approach referred to as Platform Service Agents (PSAs). The PSA works with the bus manager of the system software for that platform variant and modifies the system resources as needed. The PSA isolates specifics of the platform, so that the bus manager need not be modified. Because the PSAs themselves are outside of the kernel, are downloadable, and easily created for platform variants, new platforms can be supported without modification or re-release of the system software kernel.

Abstract: An expansion enclosure allows additional expansion cards to be used with a computer system. The enclosure exhibits a small footprint (e.g., one rack unit, or 1¾ inches) for installation in a rack or other area in which space is limited. The enclosure accepts one or more (e.g., four) expansion cards, which are connected to a removable expansion card cage. The removable cage forms part of the structure of the enclosure and provides strength and rigidity. A stabilizer may be removably but securely installed in the enclosure to stabilize or hold the removable cage as a card is installed in or removed from the cage.

Abstract: A system is disclosed for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition and a clear condition. The system includes an array of interconnected swap modules organized in a series of swap stages, each swap module having two inputs and two outputs. Each swap module is configured to receive at each input a data unit and associated mask bits and couple the data units to the respective outputs in relation to the associated mask bit's condition.

Abstract: A graphics system comprising a rendering engine, a sample buffer and a filtering engine. The rendering engine receives graphics primitives, generates sample positions, computes a depth value and color values for each sample position interior to each primitive. The blur value is assigned to each sample based on its depth value relative to an estimate of the concentration depth of the viewer. The per-sample data are stored in the sample buffer. The filtering engine reads samples in a neighborhood of a current filter position, and filters the samples to generate a video output pixel which is transmitted to a display device. The filtering engine applies to each sample in the neighborhood a corresponding filter function. The filter function has a spatial cutoff frequency determined by the sample's blur value.

Abstract: A method for verifying on-chip decoupling capacitance by formulating and solving a linear problem. Further, a software tool for determining decoupling capacitance on a computer chip using a linear problem. Further, a method for designing an integrated circuit such that there is enough decoupling capacitance on the integrated circuit.

Abstract: The present invention is a method and apparatus for characterization of electronic circuitry. Electronic systems rely on correct circuitry to function properly. Thus, a testing process is utilized to ensure correctness of circuitry. Some testing methods require multiple steps to test connectivity and correctness of circuitry. These methods are inefficient in some applications. The present invention improves efficiency of the testing process of some electronic systems. One embodiment of the present invention injects a known current into a circuit at a test point by providing a known voltage across a known resistance. The voltage at the test point is measured and the circuit is characterized by a plot of the known voltage minus the measured voltage with respect to the measured voltage. One embodiment is used to improve efficiency in testing advanced functional testers.

Abstract: A dynamic sense amplifier is provided that reduces the amount of time required to perform a memory cell restoration in a DRAM following a read operation. The dynamic sense amplifier can be isolated from the bit lines that it is sensing to avoid the capacitance affects of the bit line during a restoration operation. By avoiding the capacitance effects of the selected bit line during a restoration operation the dynamic sense amplifier is able to restore the just read memory cell to its original state in a more efficient manner.

Abstract: A method, computer program, signal transmission and apparatus for trusted verification of instructions in a module of a computer program first determine whether a suspect module to be loaded is from an untrusted source, such as on the internet. If from an untrusted source, the suspect module is loaded and one-module-at-a-time pre-verification is performed on the suspect module before linking. If the suspect module passes such pre-verification, the module is stored in a cache.

Abstract: A method and system that manage upgrades in a high-availability computer system by viewing the upgrade process as driving the system between a succession of stable configurations. The mechanism used by a described embodiment is an availability manager that is capable of ascertaining the state of each component and driving it toward a goal state by driving toward a succession of desired stable configurations. A high-level orchestration agent instructs the availability manager when a stable configuration has been reached and it is time to drive toward a next stable configuration.

Abstract: A method for searching a computer directory database is disclosed. The method compares a first and second filename strings, the comparing operating in reverse order, from the end of the strings towards the beginning until either the entirety of the strings has been compared or a mismatch has been found.

Abstract: Improved techniques for providing users and application programs with access to data stored in computer systems are disclosed. The improved techniques are particularly well suited for use in computer systems where data can be logically organized in files presented in a file system. A multilevel caching system suitable for storing information relating to files in the file system is provided. The stored information can include file references suitable for locating files in the file system as well as other useful information about the file system. The multilevel caching system provides the ability to implement various caching strategies at different levels and increases the probability of cache hits when seeking to locate files in a file system. Accordingly, relatively expensive read operations to persistent storage devices can be minimized when locating files in the file system.

Abstract: A system and method for transmitting embedded applications over a network is disclosed, wherein a user of a computer-controlled network client, such as a remote control device used for controlling a network of computer-controlled home entertainment devices, or a Web browser running on a Web client, can request and receive compound documents that include embedded applications and/or data files that can only be processed (i.e., imaged or played) by handlers that are not resident on the client. In addition to embedded documents, the compound documents that are transmitted over the network can reference flat files (e.g, image, audio, or text files), and other compound documents. Whenever a client receives a compound document, the client determines whether it has access to all of the documents referenced in the compound document and, if not, requests the documents to which it does not have local access.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.