Abstract: A centralized database and test coverage framework tools are provided to allow developers to conduct sophisticated test coverage analysis. When testing of application code occurs, information regarding line execution by each of the tests is stored in a database file unique to the corresponding test. The information contains details on how many times each line was executed during the corresponding test. The database files each may be stored in a unique subdirectory and may be grouped in clusters specified by a developer. The storing may include executing a general purpose data collector with a database location and a cluster name as parameters. Then, test coverage results may be displayed to a user by presenting the application code. A corresponding number of executions for any line in the application code which is clicked on by a user may be displayed. This allows for dynamic source code navigation.

Abstract: A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

Abstract: Performance of an integrated circuit design, whether embodied as a design encoding or as a fabricated integrated circuit, can be improved by selectively substituting low Vt transistors in a way that prioritizes substitution opportunities based on multi-path timing analysis and evaluates such opportunities based on one or more substitution constraints. By valuing, in a prioritization of substitution opportunities, contributions for all or substantially all timing paths through the substitution opportunity that violate a max-time constraint, repeated passes through a timing analysis phase can be advantageously avoided or limited. In addition, by recognizing one or more constraints on actual low Vt substitutions, particular noise-oriented. constraints, the scope of post substitution design analysis can be greatly reduced. In some realizations, substitutions are performed so long as a leakage current budget is not expended.

Abstract: A method and system are provided for authenticating users in a client-server system in a way that allows a user to sign-on to numerous servers using a different password for each server, while still only having to remember a single master password. According to one aspect of the invention, a client generates a first set of server-specific authentication information for a first server based on master authentication information stored at the client and data associated with the first server. The client then supplies the first server-specific authentication information to the first server to access restricted resources controlled by the first server. The client generates a second set of second server-specific authentication information for a second server based on the same master authentication information. However, to generate the server-specific authentication information for the second server, the master resource information is combined with data associated with the second server.

Abstract: An interface in an integrated circuit allows an LSSD storage element and a non-LSSD storage element to function together in the same scan chain. The interface has a data lock-up module, a test enable module, a master observe module, and a clock generator module. The data lock-up module latches data to be scanned into the integrated circuit through the scan chain. The test enable module indicates the status of a tester for testing the integrated circuit. The clock generator module generates a write clock and separate, non-overlapping master and slave scan clocks for a master latch and a slave latch in the LSSD storage element. The master observe module selectively asserts the slave scan clock prior to the master scan clock in order to latch the initial data bit appearing at the master latch.

Abstract: A system and method for generating random numbers utilizing a shared or distributed source of entropy is disclosed. In one embodiment, the invention allows networked computers to generate and share entropy in proportion to the need for random numbers utilized to initialize the internal state of random number generators residing on the computers. A shared session key generated during communications between a first and second computer is appended to the current internal state of the random number generators residing on the computers to create a bit string. The bit string is then mixed or hashed using a one-way “hash” function such as message digest function to produce a mixed bit string. At least a portion of the mixed bit string is then used to reinitialize the internal state of the random number generators residing on the computers.

Abstract: The present invention discloses methods and apparatus for installing printed circuit boards within an electronic assembly. One embodiment of the present invention is an electro-magnetic interference shielding apparatus for an electronic assembly comprising a shielding partition that separates a first compartment from a second compartment. The apparatus further comprises a top enclosure capable of engaging with the shielding partition to form a plurality of contact seams. The contact seams are capable of restricting electro-magnetic interference from passing through the shielding apparatus. The top enclosure can be capable of tool-free installation and removal to provide access to the interior of the electronic assembly.

Abstract: An on-chip voltage sensor that selectively eliminates noise from a voltage measurement is provided. The on-chip voltage sensor has resistive and capacitive components in the voltage divider, thus allowing a voltage on a section of a computer chip to be measured exclusive of high-frequency noise. Further, a method for measuring a voltage on a section of a computer chip using a voltage divider having a resistor and a capacitor is provided. Further, a computer chip having an on-chip voltage sensor is provided. Further, a method and apparatus for observing voltages at multiple locations on an integrated circuit.

Abstract: A data storage system includes a computer coupled to a non-volatile storage, such as a disk drive. The computer includes a block cache for storing cached copies of data blocks, and a hash table that stores hash values corresponding to the data blocks. Prior to writing back a modified cache block to the non-volatile storage, a log recorder of the computer stores an updated hash value corresponding to the modified cache block within a write-ahead hash log, which is also contained in non-volatile storage. The log recorder creates a log record including an updated hash value and an address corresponding to a modified cache block. The log recorder additionally maintains a first pointer value indicative of log records that have been stored to the write-ahead hash log, and a second pointer value indicative of the most recent log record stored in the write-ahead hash log for which a corresponding modified cache block has been stored to the non-volatile storage.

Abstract: A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors.

Abstract: A system is described for rearranging an input data word in relation to a mask word, the data word comprising a plurality of input data units in a series of input data unit positions, each associated with a respective one of a plurality of bits of the mask word in a series of mask bit positions, each mask bit having one of a plurality of conditions, to provide an output data word comprising a plurality of output data units in a series of output data unit positions. The system comprises a control module and a shift module. The control module is configured to identify, for each output data unit position, the number of bits in bit positions in the mask word to one end of that bit position which have one of the conditions, and the number of bits in bit positions to another end of the mask word have another of the conditions.

Abstract: A system for recreating a data background to test memory designs for macros includes a macro, a first multiplexer, and a second multiplexer. The macro includes a plurality of flip-flops. The first multiplexer has a first input coupled to the macro output and a second input coupled to an inverted version of the macro output. The first multiplexer receives a control signal that selects between the macro output and the inverted version of such output to produce a first multiplexer output. A second multiplexer, coupled to the first multiplexer output and a normal scan input signal, receives a select signal that selects between the first multiplexer output and the normal scan input signal to generate a second multiplexer output, which is coupled to the macro input. A method for recreating a data background to test memory designs for a macro size defined by a plurality of flip-flops also is described.

Abstract: An integrated circuit that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Further, a method for increasing an amount of decoupling capacitance on a circuit through preferential shielding is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract: One embodiment of the present invention provides a system that facilitates performing a mask-driven multiplication operation between arithmetic intervals within a computer system. The system first receives interval operands, including a first interval and a second interval, to be multiplied together to produce a resulting interval. Next, the system uses the operand values to create a mask. The system uses this mask to perform a multi-way branch to the code for the interval operands. In one embodiment of the present invention, creating the mask additionally involves: determining whether the first interval and/or second intervals are empty, and modifying the mask so the multi-way branch directs the execution flow of the program to appropriate code for this case. In one embodiment of the present invention, if the first interval is empty or if the second interval is empty, the multi-way branch directs the execution flow of the program to code that sets the resulting interval to be empty.

Abstract: A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as an M×N array using two drivers. A first and a second driver are used to drive first and second signals at slightly different frequencies on a first and a second display conductor. A plurality of pixels, coupled between the first and second display conductors, is addressed according to a pixel location in which the first signal is approximately in phase with the second signal. The pixel scan rate is proportional to the difference between the first and second signal frequencies. The first and second conductors may contain a plurality of delay elements and tap-off points. Conducting lines may be terminated by their characteristic impedance to prevent any reflection of the traveling signals.

Abstract: An apparatus and method for finding suitable transistor sizes for complex logic networks. An electrical “logical effort model” of a logic circuit is made by replacing each logic element with a simple electrical model and retaining the wiring topology of the original circuit. The logical effort model is a DC circuit with parameters that depending only on the gain chosen for the logic elements in the critical path, the stray capacitance of critical connections, and the logical effort of each logic element. A circuit simulation of the logical effort model produces voltages proportional to desired transistor widths. In working on the electrical model, the circuit simulator merely solves the set of simultaneous equations implied by the model. Alternate methods are also described.

Abstract: A graphics system and method for reducing redundant transformation calculations and lighting calculations performed on vertices that are shared by more than one geometric primitive is disclosed. The reduction in redundant calculations is accomplished by delaying the formation of geometric primitives until after transformation and lighting has been performed on the vertices. Transformation and or lighting are performed independently on a vertex-by-vertex basis without reference to which geometric primitives the vertices belong to. After transformation and or lighting, geometric primitives may be formed utilizing previously generated connectivity information. The connectivity information may include mesh buffer references, vertex tags, or other types of information.

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by 2using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

Abstract: A method and system is provided to uniquely identify a remote method to invoke on a server using a hash value computed from the method signature sent from the client to the server with the call request. When a client wishes to invoke a remote method located on a server, the client sends a hash value identifying the remote method to the server in the “remote method invocation” (RMI) call. In one implementation, this hash value is created by applying a hash function to the method string name and the parameter type list and possibly the return type. When the server receives the RMI call, the server identifies which method is being called using the received hash value. The server maintains a mapping of hash values to their associated remote methods located on the server and references the correct method using the hash value. Additionally, in one implementation, the server creates the mapping table dynamically when a remote object is created.

Abstract: An improved mechanism for processing client requests is disclosed. The first time a client request for a particular resource is received by a server, it is processed by stepping through a configuration file, and selectively executing directives specified in the configuration file. As the request is processed, a list of executed directives is compiled. This list of directives is stored for future reference. The next time a request for that same resource is received, the configuration file is not consulted. Instead, the stored list of directives is accessed and used to process the request. More specifically, all of the directives on the list are executed to process the request. Processing the subsequent request in this way eliminates much of the overhead associated with request processing. There is no need to open or to step through the configuration file, and there is no need to step through the directives themselves.