Abstract: A method for designing a software program including multiple modules includes defining an initialization sequence wherein each of the modules is initialized according to a predetermined order. The method also includes defining calling order constraints wherein a first module may call a second module if the first module succeeds the second module in the allowed order. The method also includes creating a program specification for the software program. The program specification includes a module specification for each of the modules and each module specification indicates other modules called by an implementation of the module. According to one aspect, one of a plurality of initialization sequences is selected based upon the presence of one or more markers in a memory.

Abstract: Versioning may be utilized in a knowledge base decision tree in order to provide several useful features. To accomplish this, when a decision tree is traversed, the decision tree representing a knowledge base and having non-leaf nodes with one or more branches representing possible symptoms, and leaf nodes with no branches, branches may be followed corresponding to symptoms experience by the application until a leaf node is reached. This traversal may be recorded as a version, with subsequent traversals having a different version. This allows a user to rerun performance tuning either from the beginning or from an earlier node without having to re-enter information already provided. It also allows a user to resume the performance tuning should he be interrupted in the middle, such as by a crash or by having to halt a long traversal.

Abstract: The clock signal is the dominant source of electromagnetic interference (EMI) for many electronic devices. EMI generated by an electronic device must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. EMI emissions are reduced by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. Implementations of the tunable delay lines are provided. In one implementation, a tunable delay line includes a first pipeline, a second pipeline, and a coupling mechanism for coupling the first pipeline to the second pipeline at various transfer points. The forward latency of the second pipeline is longer than that of the first pipeline.

Abstract: A method for dynamic personal identification number (PIN) management includes selecting a PIN comprising at least one picture category ID, determining a correspondence between at least one entry token and the at least one picture category ID and creating a picture category ID list in response to an access request. The picture category ID list includes the at least one picture category ID. The method also includes providing the picture category ID list for displaying a composite image including pictures based on the picture category ID list, receiving an entry token list in response to the providing and granting access to the service based upon whether at least one entry token in the entry token list corresponds to the at least one picture category ID. According to one aspect, the method also includes providing instructions to the user regarding which pictures are based on the PIN.

Abstract: A server has a memory and an analyzer. The memory stores a library of symptom descriptions, a library of corresponding diagnoses, a library of corresponding remedies, and a library of corresponding probes. The analyzer is coupled to the memory and has an identifier, a comparator, and a reiterater. The identifier identifies at least one symptom of an application to be probed based on an input. That input can either be a user input describing the symptoms of the application or symptoms previously already identified. The comparator compares the symptoms of the application with the library of symptom descriptions. The reiterator reiteravely operates the identifier on the comparator until the symptoms correspond with a diagnosis from the library of corresponding diagnoses.

Abstract: Solutions to a value recycling problem that we define herein facilitate implementations of computer programs that may execute as multithreaded computations in multiprocessor computers, as well as implementations of related shared data structures. Some exploitations of the techniques described herein allow non-blocking, shared data structures to be implemented using standard dynamic allocation mechanisms (such as malloc and free). Indeed, we present several exemplary realizations of dynamic-sized, non-blocking shared data structures that are not prevented from future memory reclamation by thread failures and which depend (in some implementations) only on widely-available hardware support for synchronization. Some exploitations of the techniques described herein allow non-blocking, indeed even lock-free or wait-free, implementations of dynamic storage allocation for shared data structures.

Abstract: An enclosure for an electronics assembly, comprises (i) a housing (1) having a recess (36); and (ii) a module (40) for holding one or more components of the assembly, the module being insertable into the recess by sliding, and removable therefrom by sliding in a direction opposite to the direction of insertion; and (iii) a spring retaining element (48) located in one of the housing and the module, the element being in the form of a resiliently deformable arm that engages the other of the housing and the module when the module is inserted into position within the recess in order to prevent removal of the module from the recess. The arm can be manually bent to release the module from the recess, but the housing or the module allows a degree of movement of the retaining element during release of the module that is insufficient to allow the arm to bend beyond its elastic limit. The enclosure enables the module to be held firmly in place, but allows quick and easy release for maintenance of the assembly.

Abstract: A system and method is disclosed for synchronizing threads of execution within a distributed computing environment. Threads of execution within a computer spawn additional threads of execution on separate computers within the distributed computing environment. Each thread may compete for shared resources within the computing environment, thereby creating a need to avoid deadlocks among the local threads. Whereas locals thread exists within a single computing platform, logical threads are created to relate local threads to each other and thereby span the platforms on which the local threads reside. Distributed monitors are created to control access to shared resources by local threads based on logical thread affiliations. Locks within the distributed monitors are assigned to logical threads instead of local threads. Local threads that are each part of the same logical thread will all have access to the shared resource when the lock is assigned to the logical thread.

Abstract: Apparatus is disclosed for viewing computer generated images and for tracking the positions of the user's head and hand. One alternative of the apparatus includes a frame element, versatilely mountable, with sensors for the head tracking of a user whose bodily movement is constrained to a small area. Short range and inexpensive sensors are deployed for tracking the position of the user's head; these sensors are deployed partly on a on the user's head and partly on the tracking frame. All the electronics for tracking and user input are enclosed in a mobile pack. In another alternative of the tracking invention natural forces such as gravity, the Earth's magnetic field, and inertia are used, so additional references. The display allows for interchangeable optical elements so that it may be tailored to suit the needs of a particular user or application.

Abstract: An optical interconnect is provided that optically connects two adjacent printed circuit boards, or electrical component. The optical interconnect includes a floating frame which is flexibly connected to one electrical component. The floating frame includes a plurality of optical guides. The optical guides are connected to the electrical component either electronically or optically. A second frame, coupled to a second electrical component also contains a plurality of optical guides. A mechanical guide assembly positions the first frame and the second frame are optically coupled. The optical guide in the second frame connects to the second electrical component providing a path for a signal from the first electrical component to the second electrical component.

Abstract: A digital data processing apparatus configured to selectively transfer data between a primary data storage element and an associated data file on a secondary data storage element. The apparatus includes a primary data storage element that stores data for access by one or more processes, as well as a non-volatile secondary data storage element. A directory stores attributes reflecting a state of one or more subsets of data in respective sets. During transfer of data between the primary data storage element and the secondary data storage element, the apparatus stores data corresponding to the attribute in a second file on the second storage element, in response to detecting the transfer and detecting the attribute indicates an atomic state corresponding to the first data.

Abstract: A functional unit is described for selectively performing a number of types of bit rearrangement operations, including a generalized bit reverse operation and a generalized shuffle/unshuffle operation, and in addition left and right unsigned shift operations and an arithmetic shift right operation. The functional unit includes a shifter array and a control signal generator. The shifter array includes a plurality of selector circuits arrayed in a number of stages for shifting bits of an input data word in accordance with control signals, the output of the last stage corresponding to a rearranged output data word. The control signal generator generates control signals in response to rearrangement operation type and pattern information.

Abstract: An electronics assembly comprises: (i) a frame (1); (ii) a motherboard (16) that is located within the frame; and (iii) one or more daughterboards (20) that extend in a plane generally perpendicular to the plane of the motherboard. The motherboard has a protective shield (40, 52) that extends over the major surface of the motherboard that is oriented toward the or each daughterboard. The shield has one or more apertures (54) therein to allow electrical connection between the motherboard and the or each daughterboard.

Abstract: One embodiment of the present invention provides a system for encoding a dataword into a current codeword within a stream of codewords, wherein each codeword in the stream has a substantially equal number of ones and zeros, and wherein each transition between codewords involves a substantially equal number of rising and falling transitions. The system creates the current codeword from the dataword and a preceding codeword in the stream by inverting substantially half of the zero bits of the preceding codeword and inverting substantially half of the one bits of the preceding codeword. This is accomplished by using the dataword to select one bits and the zero bits to invert; determining locations of the one bits and zero bits in the preceding codeword; and then inverting the selected one bits and zero bits in the preceding codeword to form the current codeword.

Abstract: An electronics assembly comprises: (i) a frame (1); and (ii) a motherboard (16) that is removable from the frame. One or more motherboards (20) extend in a plane generally perpendicular to the plane of the motherboard; and a number of elongate guides (24) are provided for the daughterboards to enable each daughterboard to be moved toward the motherboard into engagement therewith and away from the motherboard out of engagement therefrom. The motherboard (16) has at least one location element (32) thereon, which can engage one of the elongate guides (24) in order to locate the guides and the motherboard with respect to one another. This assembly enables accurate positioning of the daughterboards and the motherboard for forming electrical connections between them even where large tolerances are present in other parts of the assembly.

Abstract: Low voltage latches are designed such that all the transistors included in the latch are low threshold transistors and the low threshold transistors have the same channel dimensions, i.e., the same channel length and width. In order to meet this requirement and still provide a feedback signal of sufficient strength, latches according to the invention include feedback stages with multiple inverters. By using only transistors of the same channel length and width in the latches of the invention, the voltage scalability of the latches of the invention is increased significantly over that of prior art latches.

Abstract: A shared write back buffer for storing data from a data cache to be written back to memory. The shared write back buffer includes a plurality of ports, each port being associated with one of a plurality of processing units. All processing units in the plurality share the write back buffer. The shared write back buffer further includes a data register for storing data provided through the input ports, an address register for storing addresses associated with the data provided through the input ports, and a single output port for providing the data to the associated addresses in memory.

Abstract: In a message-passing, queue-oriented bus system, a separate interrupt work queue assigned to each interrupt line for each PCI device sends interrupt information packets from the device to the host. To prevent an interrupt from being transmitted before another DMA data write has been completed, interrupt requests are held on the interrupt work queue until all outstanding data transfer requests have been acknowledged. A special data structure called an interrupt scoreboard is created for each interrupt work queue entry associated with a DMA write in order to track the DMA data transfer. When an interrupt is received, the interrupt scoreboard acquires a “snapshot” of the state of the pending data requests and tracks the pending DMA transfers. When acknowledgement messages have been received for all pending DMA transfer requests, then the interrupt data packet is transmitted so that the interrupt can be serviced.

Abstract: A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses.

Abstract: The clock signal is the dominant source of electromagnetic interference (EMI) for many digital electronic devices. EMI generated by these electronic devices must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. The present invention seeks to reduce EMI emissions by phase-modulating the clock signal using tunable delay lines. Phase modulation causes a spreading of the energy spectrum of the clock signal thereby reducing EMI emissions. In addition, the present invention is capable of generating a wide energy spectrum in a short time interval. Furthermore, the present invention can be similarly applied to other signals which exhibit a periodic or timing nature due to a correlation with the clock signal.