Abstract: Methods and apparatus for maintaining connectivity of nodes in a wireless LAN. Accordingly, the present invention provides a method and apparatus for maintaining connectivity in a wireless LAN. The LAN is divided into a plurality of cells. Each cell is occupied by at least one access point for communicating information between the cells, and at least one node for communicating via the LAN through the access points. To initiate a handoff from a first access point with which the node is currently communicating, the node first selects a second access point as a candidate for handoff. The node then communicates an instruction to the first access point instructing the first access point to relay a request to the second access point that the second access point accept a handoff of the node from the first access point. The first access point then relays the request to the second access point.

Abstract: A performance counter to monitor a plurality of events that may occur in a component within a computer system during a monitoring period or testing period. The monitoring results, which are provided upon completion of the performance testing, may be used to provide histogram representations of the component performance. In one embodiment, the performance counter comprises a first storage, a second storage, programmable control logic, and a counting mechanism. The first storage is configured to store information indicative of a plurality of events to be monitored and the monitoring period for each event. The second storage is configured to store counting results obtained during the testing period. A counting mechanism, which is coupled to the second storage, is configured to monitor the occurrence of the events in the component under test. The counting mechanism is coupled to the control logic and the control logic is coupled to the first storage.

Abstract: A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: A method and computer graphics system for clip testing using clip bits stored in a general-purpose register for each vertex of a geometric primitive. In one embodiment, a rendering unit or other processor sets bits in a clip bits register for each vertex of a geometric primitive. Each bit indicates whether the vertex is inside or outside of a clipping boundary with respect to a particular clipping plane. A frame buffer controller or other graphics processor performs clip testing on the entire geometric primitive by performing Boolean operations on the clip bits. The frame buffer controller may trivially accept or trivially reject the primitive based on the clip testing. If the primitive cannot be trivially rejected or trivially accepted, then the frame buffer controller sends an interrupt to the rendering unit. The rendering unit reads an exception register to determine that the reason for the interrupt is the need to clip the primitive.

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Abstract: A method and apparatus for delivering analog data on demand from a multiple channel digital media server are provided. A digital data stream is admitted to a media server in response to a user selecting a program for playback. A data structure is initialized and maintained for the admitted digital data stream, the data structure controlling the conversion of the admitted digital data stream to an analog data stream on the converter channel. The data structure initialization comprises initializing a state of the admitted digital data stream and a control bit cache flag at a first requested state change for the admitted digital data stream, typically a play command issued by the user. A number of control bits of a converter channel are also initialized using the converter control channel at a first requested state change of the admitted digital data stream. The data structure prevents the reinitialization of the control bits of the converter channel during state changes of the admitted digital data streams.

Abstract: A network device that can be implanted in a subject is described. The device is configured to communicate over a computer network. In one embodiment, the device of the invention includes an internal interface in physiological communication with the subject. The internal interface is coupled with, and configured to send signals to, a processor. The processor is configured to receive and process the signals, and is further configured to communicate over a computer network with another such device. Such devices can be used to monitor and communicate information regarding a host's physiological status, monitor and/or control artificial organs and prosthetic devices, and/or dispense medication.

Abstract: Mapping rules for use in mapping data between a relational model and an object model. A user interface permits a programmer or other person to enter the mapping rules, and a mapping tool converts data between the relational model and the object model according to the mapping rules.

Abstract: The present invention describes a method and system for providing cluster replicated checkpoint services. In particular, the method provides cluster replicated checkpoint services for replicas of a checkpoint in a cluster. The cluster includes a first node and a second node, which are connected to one another via a network. The replicas include a primary replica and a secondary replica. The method includes managing the checkpoint that contains checkpoint information, and creating the primary replica in a memory of the first node. The primary replica contains first checkpoint information. The method also includes updating the primary replica so that the first checkpoint information corresponds to the checkpoint information, creating the secondary replica that contains second checkpoint information in a memory of the second node, and updating the secondary replica so that the second checkpoint information corresponds to the checkpoint information.

Abstract: A system, method and computer program product for compiling a source file and to generate a unitary data structure (UDS) containing information relating to symbols and associated global registers. The UDS permits assessment of symbol conflicts for global registers. The compiler also generates object files from related source files. The object files include the global symbol information relating to particular global registers, to enable diagnosis of conflicts between global symbols and registers.

Abstract: A high performance network interface receives network traffic in the form of packets. The network interface parses one or more headers of a received packet in order to determine whether the packet has been formatted with a pre-selected protocol. If so, one or more efficient enhancements in the processing of a packet may be enabled for the packet. During parsing, header data that may be useful in the processing enhancements may be saved. A packet conforming to one or more of a set of pre-selected protocols may be more completely parsed than a packet not conforming to any of the pre-selected protocols. Instructions for parsing a packet to determine a protocol and to extract useful data are stored in a writeable random-access memory. The instructions may be replaced, modified or supplemented depending upon the composition of network traffic and the protocols selected for enhanced processing.

Abstract: The alarm manager display in a distributed network management system is arranged to have two modes of operation. In one mode of operation, the alarm manager display automatically scrolls when new events arrive. If there are sorting criteria defined, the alarm manager window scrolls either up or down depending on the sort order so that when new events arrive, they always appear on the screen. In the second mode of operation, the alarm manager window does not scroll when new events arrive. The scroll bar operational modes are selectable by an operator from a menu. In accordance with another embodiment, a special attribute is added to the alarm manager configuration file. This attribute is read when the alarm manager is started and places the alarm manager into the operational mode in which it was last used.

Abstract: Remote access to objects such as beans is provided by mapping objects onto an HTML page at the network station at which the objects are located. An HTML generator running on the same virtual machine is used dynamically to map the beans onto the HTML page. Remote access for browsing the modifying the object is then possible using a web browser supporting HTTP or HTML protocols without having to specially modify an object to permit access, for example by the provision of remote access code in the object. An application for remote bean access is in the context of a network agent for a network management system.

Abstract: A system is disclosed for performing floating point computation in connection with numbers in a base floating point representation (such as the representation defined in IEEE Std. 754) that defines a plurality of formats, including a normalized format and a de-normalized format, using a common floating point representation that defines a unitary normalized format. The system includes a base to common representation converter, a processor and a common to base representation converter. The base to common representation converter converts numbers from the base floating point representation to the common floating point representation, so that all numbers involved in a computatoin will be expressed in the unitary normalized format. The processor is configured to perform a mathematical operation of at least one predetermined type in connection with the converted numbers generated by the base to common representation converter to generate a floating point result in the common representation.

Abstract: A clock buffer circuit is disclosed. The clock buffer circuit is included in each sub-block of a clock distribution structure in an integrated circuit. Each clock buffer circuit comprises a plurality of driving inverters, and each clock buffer circuit presents an equal input load to the previous driver, regardless of the amount of load in the sub-block circuit. In each sub-block, the clock buffer circuit is connected to provide an output including the combined signals of a portion of the inverters. The portion is approximated by the load of the circuit in the sub-block divided by the load of the circuit in the sub-block having the greatest load of any sub-block. The outputs of inverters not connected to the load of the sub-block circuit are wired to power and ground terminals. Each driving inverter may comprise a pMOS FET paired with an nMOS FET. A method for designing such a clock buffer circuit is also disclosed.

Abstract: A volatile field programmable gate array (FPGA) having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the FPGA in configuration data memory. On FPGA reconfiguration, for example on power-up, the encrypted configuration data is supplied to an input of the FPGA. In the FPGA, the configuration data is first decrypted by a decryption algorithm embedded in logic, the algorithm using as an operand a decryption key stored in the FPGA in a non-volatile memory, for example EEPROM. The decrypted configuration data is then distributed to the volatile functional portion of the FPGA in a conventional manner. The functional portion may be SRAM. With this design, unauthorized reading of the configuration data of the FPGA by observation of the stream of configuration data transmitted to the FPGA from the external memory, for example during power-up, will only result in encrypted configuration data being obtained.

Abstract: One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage.

Abstract: A support mechanism for a part of a circuit card includes a support member (slide) which forms a fixed part. The support member defines a guide. It also includes a slideable member for engaging the circuit card. The slideable member (slider) is slideable along the guide to a position for engaging the card. The slider defines a jaw for engaging the circuit card. The jaw can be provided with a protrusion for engaging with a hole in the corner of a circuit card, for example a PCI card. The mechanism enables the supporting of cards of different lengths due to the slideability of the slide along the guide. The guide and the slider can be formed with inter-engaging structures of appropriate shapes, for example, co-operating dovetail shapes.

Abstract: A digital data processing system comprises at least one subsystem comprising a plurality of resources, such as a storage subsystem comprising a plurality of drive modules, and a host processor. The host processor is connected to the drive modules through an interconnection which has a topology in the form of a loop. The interconnection has at least one configuration switch that is selectively configurable to a pass-through mode, in which the topology comprises the entire loop, or a bypass mode, in which the topology comprises a portion of the loop including the host processor and, possibly, at least one of the drive modules in the storage subsystem. The host processor can selectively condition the configuration switch into the pass-through mode or said bypass mode to connect more or fewer drive modules into the loop.