Abstract: A computation unit computes a division operation Y/X by determining the value of a divisor reciprocal 1/X and multiplying the reciprocal by a numerator Y. The reciprocal 1/X value is determined using a quadratic approximation having a form: Ax2+Bx+C, where coefficients A, B, and C are constants that are stored in a storage or memory such as a read-only memory (ROM). The bit length of the coefficients determines the error in a final result. Storage size is reduced through use of “least mean square error”techniques in the determination of the coefficients that are stored in the coefficient storage. During the generation of partial products x2, Ax2, and Bx, the process of rounding is eliminated, thereby reducing the computational logic to implement the division functionality.

Abstract: A processor includes a “four-dimensional” register structure in which register file structures are replicated by N for vertical threading in combination with a three-dimensional storage circuit. The multi-dimensional storage is formed by constructing a storage, such as a register file or memory, as a plurality of two-dimensional storage planes.

Abstract: A computer video display system and method is disclosed. The computer video display system includes a frame buffer for storing a multiplicity of view points of a model to be displayed, a measurement device for measuring an aspect of the user's movement, a view point device for ascertaining a point of view of the model to be displayed in response to the measurement device, a computational device for modifying the view point according to a predefined algorithm, an access device for accessing the appropriate display information from the frame buffer, and a head mounted display for displaying the selected view point of the model. During operation, the measuring device, the view point device, and the computational device continuously update the view points of the model in response to movements of the user. In response thereto, the access device traverses the frame buffer and provides the updated display information to the head mounted display.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator; a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser, and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: One or more boost circuits are included within each row of CAM cells to increase the charging rate of its match line during match conditions. The CAM cells in each row control corresponding match transistors connected in series between a supply voltage and a match line. The match transistors collectively form a NAND match circuit. A boost circuit connected between a supply voltage and ground potential is coupled to a midpoint of the NAND match transistor chain. During compare operations, if all CAM cells match, all match transistors turn on and pull the match line toward the supply voltage. As the voltage at the midpoint of the match line reaches a threshold voltage, the boost circuit provides an additional charging path to more quickly charge the match line. If any CAM cell mismatches, its match transistor turns off and isolates the match line from the supply voltage.

Abstract: The present invention provides a mechanism for enabling memory allocation operations to be deterministic. According to the invention, determinism is achieved by first pre-allocating a contiguous memory space, and then using that memory space to perform subsequent memory allocation operations. Because the subsequent memory allocation operations are performed using memory space that has already been allocated, it is ensured that the allocation operations will not trigger a garbage collection operation. Also, because the pre-allocated memory space is contiguous, there will be no fragmentation concerns. Thus, the present invention eliminates the two major causes of non-constant allocation times. By doing so, the present invention makes it possible to achieve determinism in a dynamic memory allocation system.

Abstract: A system and method for determining a routing of cables between devices within a computer chassis. The method comprises signaling, for each of the devices, deactivation of a selected signal line of each cable. Then, one of the devices is requested to activate its selected signal line for one of the cables. The selected signal line is coupled to an input/output (I/O) data port of a driver circuit associated with the devices. The voltage on the I/O data port is sensed to determine which device is coupled to and in control of other device(s).

Abstract: A scalable performance storage architecture. The input/output operations per second (iops) and the data transfer rate are two very important performance measures of a storage system. Command and status information require little bandwidth, whereas data transfer is limited by the bandwidth of the storage controller busses, memory, etc. This invention first organizes the storage controller architecture into its functional units. The data paths that connect various functional units (for example, switching unit, parity logic, memory module, etc.) may then be sized to the required bandwidth. This effectively makes the iops and bandwidth capability of a storage controller scalable independently of each other, resulting in a selectively scalable storage system architecture. The system designer may increase the number of CPU's in a storage controller (for more iops) or the data bandwidth (for high aggregate data transfer rate) independently of each other.

Abstract: A method and apparatus for maintaining source control for successive versions of software where modifications are made to an initial version that are not included in the successive versions. When the initial version is received, it is modified and both the initial version and the modified initial version are placed under source control in the form of a source tree. When a new version of the software is received, the invention determines differences between the initial version and the new version and creates a record of differences between the initial version and the new version. The differences are integrated into a copy of the initial version and are then incorporated to the modified initial version, which is then incorporated to a modified initial version to yield a modified new version. In some embodiment of the present invention, the original source tree is retained in case modifications are again made to the initial version.

Abstract: Techniques for providing extensible applications arc provided. A bundle or software module can be developed that is able to install itself within an application. The software module can also inform the application upon which services the software module depends so that if the required services are not available, the application can obtain them. An activation function can be defined in the software module that registers the services provided by the software module with the application so that the services can be available to other software modules.

Abstract: A method and apparatus for storing associated data in a computing system having two or more storage devices arranged in a RAID configuration. The storage devices have a prewrite area for pre-storage of the data, and data region for persistent storage of the data. A scoreboard memory structure is created for monitoring the state of the prewrite area, and data in the prewrite area is conditionally invalidated based upon the information contained in the scoreboard memory structure. By conditionally invalidating the prewrite data, the write performance of the RAID storage system is improved.

Abstract: The present invention comprises a method and apparatus for selecting data using a graphic object such as a slider that incorporates a display area for displaying information about the data that is selected. In an embodiment of the invention, an arbitrarily sized and shaped slider for selecting data from an arbitrarily sized and shaped graphical representation related to an underlying set of data are displayed on a display screen. Each position in the display screen occupied by the graphical representation correlates to particular data from the set of data represented the graphical representation. As the slider is moved relative to the display screen, information identifying the data corresponding to the current position of a reference datum of the slider is displayed in an information display area of the slider.

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: A method of computing a square root or a reciprocal square root of a number in a computing device uses a piece-wise quadratic approximation of the number. The square root computation uses the piece-wise quadratic approximation in the form: squareroot(X)={overscore (A)}ix2+{overscore (B)}ix+{overscore (C)}i, in each interval i. The reciprocal square root computation uses the piece-wise quadratic approximation in the form: 1/squareroot(X)=Aix2+Bix+Ci, in each interval i. The coefficients {overscore (A)}i, {overscore (B)}i, and {overscore (C)}i, and Ai, Bi, and Ci are derived for the square root operation and for the reciprocal square root operation to reduce the least mean square error using a least squares approximation of a plurality of equally-spaced points within an interval. In one embodiment, 256 equally-spaced intervals are defined to represent the 23 bits of the mantissa.

Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

Abstract: The client portion of a distributed client-server network management system uses an interface designed with, and written in, a platform independent language, such as Java. This allows management application programs to be written in the platform independent language and insures their portability. Further, in accordance with another aspect of the invention, the inventive interface allows a user to query an alarm log while the alarm log record information is cached at the server so that only a small client program is necessary. This program can run on a system with minimal resources, thereby allowing a network manager to manage a network from virtually any location on the network. For example, the client management application could be written as a Java applet which could then be run on any Java-enabled browser.

Abstract: A method, system, and computer program product for synchronized thread execution in a multithreaded processor are described. Each synchronized thread refers to at least one object identified by an object identification (OID) that is shared among a plurality of synchronized threads. One of the synchronized threads is selected for execution. Upon entering the selected thread, an entry sequence indicates that the shared object should be locked by pushing its OID onto a lock stack. The operations defined by the selected thread are executed and the indication is removed by pushing the OID from the lock stack.

Abstract: A computer system and method provide networked computer users with information about which other users are task proximate to the user, thereby facilitating spontaneous communications regarding task-related, or other, issues. The information about other users is displayed in a user interface window on each computer that presents a visual representation of each user who is task proximate to the user operating the computer. Task proximity to other users may change as the user context switches between applications, and the user interface window is updated accordingly. Task proximity is determined individually by different applications. One exemplary system architecture for providing the information includes a person object representing each user, and storing the visual representation of the user. An encounter window on each computer displays the visual representations. A number of encounter-aware applications may execute on each computer.

Abstract: A number of methods, apparatus, and data structures are disclosed for managing computer processes. In one aspect, a daemon process which manages server processes includes an active server table and a locator service. The locator service can look up and register server processes in the active server table. Furthermore, the locator service can start up server processes. In some embodiments, the locator service includes a look-up object and a server process registration object which perform the tasks of the locator service. In other embodiments, methods for managing server process such as starting and registering the server processes are taught. In one specific method, a daemon process performs a variety of steps in response to receiving a look-up call for a target object. These steps include obtaining a server identifier for the target object, determining the state of a server process, and returning addressing information corresponding to the server process under which the target object will activate.

Abstract: A memory module with offset notches for improved insertion and a memory module connector for mating thereto. The connector housing includes an accommodating s space for receiving a portion of the memory module printed circuit board (PCB). A first key is disposed within the accommodating space of the housing and is positioned between the first end and the center of the housing. A second key is flirter disposed within the accommodating space and is positioned between the second end of the housing and the center. A distance between the first key and the second key is greater than 40% of the length of the housing. Either the first, second, or both keys may extend from the accommodating space beyond a top plane defined by a top side of the accommodating space of the housing. The memory module comprises the PCB with a first notch positioned between the first end of the PCB and the center of the PCB. A second notch is positioned between the second end of the PCB and the center of the PCB.