Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

Abstract: A method and system for establishing a shared secret between a plurality of devices using an authentication token. An authentication token is used to establish a shared secret between a local device and a remote device to provide user authentication, data encryption, and integrity protection. The authentication token may be used in a variety of ways to authenticate a user. First, a time-synchronized authentication token can generate a first character string that is communicated to a workstation. The workstation can manipulate the first character string to generate a second character string and send the second character string to a server. The server then compares the second character string with a plurality of possible matching character string values and determines the first character string. In another implementation, a challenge from a server can be received and processed by a challenge-response authentication token to generate a character string.

Abstract: During burst write transactions, a memory accepts data over an address bus after an address has been received. In order to accept data over the address bus, the memory temporarily stores the data received over the address bus in an internal data buffer. The internal data buffer then transfers the data to an array upon completion of the write transaction. During burst read transactions, the memory transmits data over the address bus during one of the four clock cycles after the address is received. In this way a burst write transaction is completed in three clock cycles instead of four. Burst read transactions are completed in four clock cycles instead of five.

Abstract: An object structure's header (40) allocates a two-bit synchronization-state field (42) solely to monitor data for implementing synchronization on that object. When the object is locked by a particular execution thread, or when one or more execution threads are waiting for a lock or notification on that object, its header contains a pointer to monitor resources in the form of a linked list of lock records (50, 52, 54) associated with the threads involved. The synchronization-state field (42) ordinarily contains an indication of whether such a linked list exists and, if so, whether its first member is associated with a thread that has a lock on the object. When a thread attempts to gain access to that linked list, it employs an atomic swap operation to place a special busy value in that lock-state field (42) and write its execution-environment pointer into the object's header (40).

Abstract: A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reliably completed even in the presence of a failure. To ensure consistent mapping and file permission data among the nodes, data are stored in a highly available cluster database. Because the cluster database provides consistent data to the nodes even in the presence of a failure, each node will have consistent mapping and file permission data. A cluster transport interface is provided that establishes links between the nodes and manages the links. Messages received by the cluster transports interface are conveyed to the destination node via one or more links. The configuration of a cluster may be modified during operation.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A method and apparatus for coupling object state and behavior in a DBMS is provided such that an object's class definition, behavior information, and state information are included in the DBMS. An object is instantiated using an object class definition, state information, and behavior information from the DBMS. In addition, an object can be stored in the DBMS by storing its class definition along with its state and behavior information in the DBMS. The behavior information stored in the DBMS can be used within and without the DBMS environment.

Abstract: Doors are implemented in an existing operating system by using a novel adaptation of existing data structures and procedures which represent and control data files of the operating system. A door is represented by a file descriptor and is managed by existing mechanisms of an operating system, such as the Unix operating system, which are also used to manage files. A door is represented by a door node, which is a novel extension of the conventional vnode structure which in turn is used in conventional operating systems to represent the state of a computer resource, e.g., a data file. A door node is adapted such that most conventional file access and control procedures, e.g., procedures open( ) and close( ), can be used to access and control door with minimal adaptation.

Abstract: Asynchronous circuitry provides a domino circuit having short cycle times and zero overhead latency. The control circuit of a datapath circuit may utilize a completion signal from the datapath circuit to develop a request signal to the datapath circuit. The request signal may also be based on a request signal from a previous stage. Using the completion signal of a stage to develop the request signal for the same stage allows the circuitry to reduce the impact of constraints that are required for the asynchronous circuitry to operate. Similarly, using the request signal from a previous stage of the asynchronous circuitry to develop the request signal for a present stage also allows the circuitry to reduce the impact of constraints required to implement the asynchronous circuitry. These techniques allow the achievement of fast cycle times while maintaining zero overhead.

Abstract: A clip testing unit within a graphics accelerator for comparing a value of a given homogeneous coordinate of a vertex position of a polygon relative to a plurality of clipping planes. The plurality of clipping planes includes both regular and guard band clipping planes. The clip testing unit includes registers for receiving and storing a W value corresponding to the vertex position, as well as a coordinate input register for receiving and storing the given homogeneous coordinate. The W value is conveyed to a guard band W generation unit, which generates a guard band W value in response thereto. The clip testing unit also includes a clip compare unit coupled to receive the W value, the guard band W value and the value of the given coordinate. The clip compare unit receives and compares the W value and the value of the given coordinate, generating one or more first clip signals in response thereto.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length decoder includes a length estimator and a length selector. The length estimator, estimates a length for each data word assuming the data word is the first member of a group. The length selector then selects the proper estimate based upon the actual length of the data word. Specifically, one embodiment of the length decoder can be used to calculate the length of instruction groups in a stack based computing system.

Abstract: A portable telephone provides a graphical user interface (GUI) using a high-resolution display. The GUI provides a Universal Mailbox for storing both electronic mail and voicemail messages, either of which can be accessed by a user from the same display screen. An automatic reply feature allows a user to initiate an outgoing reply to a received message with the touch of a button. For a reply to a voicemail message, the GUI accesses Caller ID information to automatically identify and dial out to the phone number of the sender of the original message. For an electronic mail reply, the GUI automatically displays a reply form addressed to the source address. Reply forms may be generic, custom designed for a specific source address, or provided by the sender. An advanced call control feature automatically checks an outgoing telephone number against a database to determine whether the phone number is currently appropriate.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. The invention maintains a predictor value that controls the number of stack elements that are spilled from, or filled to, the top-of-stack cache in response to an overflow trap or an underflow trap (respectively). The predictor reflects the history of overflow traps and underflow traps.

Abstract: An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated circuit comprises a plurality of active layers coupled together in close proximity. In order to produce the integrated circuit, at least two active layers are removed from their respective substrate after integrated circuit processing. Some of the methods that may be used include Silicon on Insulator ("SOI") and epitaxial etch stop ("EES") processes. After removal of the active layers, at least one via is implemented on a bottom surface of each active layer in order to establish a mechanical and electrical connection between the via and its associated metal interconnects. Thereafter, the active layers are coupled together by ultrasonic welding or through nitride lamination using Titanium Nitride for conductive regions and Silicon Nitride for insulative regions.

Abstract: A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data to a given data address and, subsequently, executes another instruction requiring a data fetch from the same address. According to this method, a write cache prevents any addressed instruction from residing in the write cache and the instruction cache at the same time. Thus, when an instruction having a store address not already present in the write cache is retired to the write cache, the write cache instructs the instruction cache to invalidate any data stored therein having a same address. The flush instruction prevents execution of any other instructions after the store at least until the store to the memory address has been allocated to a write cache of the processor, thus enabling the write cache to invalidate the subsequent instruction at the same address in the instruction cache.

Abstract: Techniques for analyzing object-oriented computer programs are provided. A snapshot of the objects that are active at a specific point in time during execution may be stored. An analysis tool may be utilized to generate hypertext documents that allow a user to analyze the active objects. Additionally, a user may compare two different snapshots of active objects at two different run-times so that, for example, new instances of a class may be easily identified.

Abstract: A method and apparatus for providing security to a server running an application program received over a network is provided. The application program, along with a source identifier is received from a source computer. Access privileges to server resources are granted based on the source identifier. The application program is loaded into a predetermined, bounded region of memory.

Abstract: Data structures, methods, and devices for facilitating servant invocation in a distributed client-server based object oriented operating system are disclosed. In one aspect of the invention, descriptor data structures, which contain a typecode indicator, a marshaling function identifier, and an unmarshaling function identifier, are used to enable modules of application code to be shared between different objects, thereby facilitating servant invocation by increasing the amount of commonized code in the operating system. In another aspect of the invention, a server invocation object is used in the execution of a method call. In still another aspect of the invention, a commonized code base is used to process typecode interpreted and compiled calls to a server process.

Abstract: A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource control mechanism in the bridge comprises: an interface for exchanging signals with one or more resource slots of a device bus that is capable of being connected to the bridge, each of the resource slots being capable of communicating with a system resource; and a register associated with each system resource, the register having switchable indicia that indicate an operating state of the associated system resource, the control mechanism being operable in use to direct signals to and/or from respective system resources of the computer system.