Abstract: A rapid method for calculating a local eye vector in a fixed point lighting unit. For a given triangle primitive which is to be projected into a given viewport in screen space coordinates, the local eye vector corresponds to a given eye position and a first vertex of the given triangle primitive. (A different local eye vector is calculated for each vertex of the given triangle primitive). The method first comprises generating a view vector matrix which corresponds to the given eye position and corner coordinates of the given viewport, where the corner coordinates are expressed in screen space coordinates. The view vector matrix is usable to map screen space coordinates to an eye vector space which corresponds to the given viewport. The method next includes receiving a first set of coordinates (in screen space) which correspond to the first vertex. The first set of coordinates are then scaled to a numeric range which is representable by the fixed point lighting unit.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism is operable to compare address and data phases of I/O accesses by the first and second processing sets. A direct memory access mechanism is operable to initiate a direct memory access operation to read from a corresponding location in each processor set into a respective dissimilar data register associated with each processing set. The bridge control mechanism is operable during the direct memory access operation to disregard differences in the data phase for the dissimilar data write access. As a result it is possible to transfer dissimilar data from the processors into the bridge in a combined (lockstep comparison) mode.

Abstract: Techniques for allocating registers when generating code is described. A snapshot is generated when generating code. The snapshot contains sufficient information to restore the state of generating code that existed at the point when the snapshot was generated so that the generation of code can proceed from that point. A first set of code optimizations is generated. In response to determining that the first set of code optimizations fails to meet efficiency criteria, the generation of code proceeds based on the snapshot without incorporating the first set of code optimizations. Feedback is generated by analyzing the allocation of registers based on the first set of code optimizations. A second set of code optimizations is based on the feedback. Feedback includes information such as the number of spills occurring based on the first set of code optimizations.

Abstract: A computer system with a multiplexed address bus that is shared by both system memory and by slave devices is described. The slave devices are incorporated into an existing system memory configuration by providing a bus controller to execute a two-cycle address sequence on the multiplexed address bus. The address sequence is followed by a transfer of data. A random latency can exist between the time of receiving address information and the time of receiving data corresponding to the address information. This random latency can be exploited by the system CPU for other computational purposes. The bus controller of the system executes multiple, or pipelined, data writes to the bus before an acknowledgement for the first data write is received. In this scheme, the acknowledgement for the first data write is typically sent during the same time period that the subsequent data writes are being received. Consequently, data transfer acknowledgements overlap data writes.

Abstract: A method and apparatus are provided which eliminate the need for an active traffic flow control protocol to manage request transaction flow between the nodes of a directory-based, scaleable, shared-memory, multi-processor computer system. This is accomplished by determining the maximum number of requests that any node can receive at any given time, providing an input buffer at each node which can store at least the maximum number of requests that any node can receive at any given time and transferring stored requests from the buffer as the node completes requests in process and is able to process additional incoming requests. As each node may have only a certain finite number of pending requests, this is the maximum number of requests that can be received by a node acting in slave capacity from any another node acting in requester capacity. In addition, each node may also issue requests that must be processed within that node.

Abstract: A just-in-time (JIT) compiler typically generates code from bytecodes that have a sequence of assembly instructions forming a "template". It has been discovered that a just-in-time (JIT) compiler generates a small number, approximately 2.3, assembly instructions per bytecode. It has also been discovered that, within a template, the assembly instructions are almost always dependent on the next assembly instruction. The absence of a dependence between instructions of different templates is exploited to increase the size of issue groups using scheduling. A fast method for scheduling program instructions is useful in just-in-time (JIT) compilers. Scheduling of instructions is generally useful for just-in-time (JIT) compilers that are targeted to in-order superscalar processors because the code generated by the JIT compilers is often sequential in nature.

Abstract: A method and apparatus for cooling an integrated circuit device mounted face-down on a package such that the device may be optically probed. The method of the present invention includes the following steps: (1) placing an optically-transparent window over the integrated circuit device to form a channel bounded by the optically-transparent window and the integrated circuit device and (2) flowing an optically-transparent fluid through the channel to remove heat dissipated by the integrated circuit device.

Abstract: The invention relates to a computer system and method thereof characterized by high airflow and low acoustic noise by separating the enclosure of the system into two sections, in which in one section cooling fans are arranged between power supply units and disk drives, the power supply units being located at the back of the section and the fans, as to the disk drives, serving as exhaust fans, and in the other section inlet fans are arranged to cool selected hardware electrical elements, such as CPU modules, PCI and graphics cards, wherein the placement of the inlet fans is selected to minimize pre-heated air and fan airflow paths are controlled and directed by an air dam to maximize the cooling effect, and noise damping material is employed in mounting the rack for the disk drives, the disk drives and fans and in forming the side walls of the enclosure.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.

Abstract: A code generating system generates, from code in a program, native code that is executable by a computer system. The code generating system may be included in a just-in-time compiler used to generate native code that is executable by a computer system, from a program in Java Byte Code form, and specifically generates, in response to Java Byte Code representative of a synchronization statement that synchronizes access by multiple threads of execution to at least one variable contained in the Java Byte code, one or more native code instructions that implements a wait-free synchronization methodology to synchronization access to the at least one variable. Since the instructions which implement the wait-free synchronization methodology do not require calls to the operating system, they can generally be processed more rapidly than other synchronization techniques which do require operating system calls.

Abstract: To cool heat-emitting electronic components, a compact, non-moving-parts compressor, an evaporator in juxtaposition to the electronic components and a condenser are mounted as a unit, preferably within a vacuum can. A heat exchanger is mounted external to the can but in proximity to the condenser. The foregoing comprise a unit which may be detachably connected to a host pump and heat exchanger. The unit may be removed from the system of which it is a part for upgrade and maintenance. All its components are thermally isolated from the ambient atmosphere to prevent water vapor condensation corrosion.

Abstract: One embodiment of the present invention provides a method and an apparatus for providing a client-side intermediary that communicates with an application on a second server computer system. The method operates by receiving a composite message at a client computer system from a first server computer system, and examining type information from the composite message. This type information specifies how the composite message is formatted, and can be used to select an application that is capable of processing the composite message. The method uses the type information to look up a network address of the application residing on the second server computer system. This address is used to forward the composite message to the application on the second server computer system. The above embodiment can be implemented within a browser on the client computer system, or within a separate application on the client computer system.

Abstract: The present invention pertains to a system and method for tracking object references in an object-oriented computing system including a number of independent computing nodes interconnected by a communications link. The reference counting mechanism tracks references to an object through the use of a messaging protocol. A server node keeps a foreign reference count for each of its objects. The foreign reference count indicates the number of remote nodes having a reference to one of the servers objects. A server node increments the foreign reference count for each object reference that it exports prior to sending it to an intended client node. A client node will send a message to the server node when it has already received the exported object reference and in response to this message, the server node decrements the appropriate foreign reference count.

Abstract: Interconnection subsystems having diverse topologies, for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system, include subsystems broadly classified into a number of general classes based on their topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: Program routines normally requiring windowed register allocation using conventional assembly code generation in a compiler are examined for eligibility for a wrapper routine optimization procedure in which wrapper routine assembly code instructions are generated in response to the application of high level programming language instructions specifying routines. If not eligible, the compiler generates assembly code instructions in a conventional way, allocating windowed registers to each routine. If the routine is eligible for wrapper routine optimization, the routine is further examined to determine whether the routine includes tail routine calls only or calls within the body of the routine. If the former, the routine is examined to determine whether local stack usage is required. For a routine having tail routine calls only and a requirement of local stack usage, wrapper routine assembly code instructions of a first type are generated.

Abstract: A dynamic down cast or cross cast is performed at run time within an object-oriented programming language such as C++. The compiler generates data structures during a compile; at run time a routine in the language support library accesses the generated data structures in order to perform the dynamic cast. Class structure information is provided in a size that varies linearly as the total number of classes in the class hierarchy. Cryptographic hashing of class names is used to provide uniqueness. The dynamic cast addresses complications in C++ due to "virtual" and "nonvirtual" inheritance. A run time type identification (RTTI) data structure is created at compile time. An offset within an object description is calculated for each sub-object of the object. Those virtual base classes that are duplicates are skipped producing a data structure that may be searched linearly as the number of classes in the hierarchy. An identifier for each sub-object is stored in the data structure along with its offset.

Abstract: The present invention provides a unique multi stack memory system to provide access to multiple portions of the method frames of a stack based computing system. In one embodiment of the invention, a multi-stack memory system includes a first stack configured to store a first frame component of a first method frame and a second frame component of a second method frame. A second stack is configured to store a second frame component of the first method frame and a first frame component of second method frame. The first frame component of the method frames can be for example an operand stack. The second frame components of the method frames can be, for example, arguments and local variable areas.

Abstract: Interconnection subsystems having diverse topologies, for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system, include subsystems broadly classified into a number of general classes based on their topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: A method and computer system are presented for monitoring a suite of product tests as they are being performed. The tests are collected in named suites of tests. The method includes providing a display and graphically displaying names of suites that have been performed and that were passed on one region of the display and graphically displaying names of suites that have been performed and that were failed on another region of the display. The method also may include allowing a user to selectively identify a name of one of the suites that has been performed and displaying additional information on the display about the selectively identified suites. The additional information may include at least names of the tests within the suite that have been performed and that were passed or failed, and may include a journal record of the performance of the selectively identified. The display may be periodically updated in a period that may be selectively chosen or modified by the user.