Abstract: Embodiments of the present invention provide a stack renaming method and apparatus for stack based processors. Using principles of the present invention, a stack can be accessed simultaneously by one or more functional units in a stack processor. The stack apparatus includes a stack renaming unit capable of renaming a logical stack address to a real stack address. Each logical stack address corresponds to a storage element in the stack renaming unit which stores a real stack address. A circular counter is used in the stack renaming unit to sequentially cycle through each of the logical stack addresses. The real stack addresses corresponding to each of the logical stack addresses can be stored out of order in the stack renaming unit. A stack control unit is coupled to the stack renaming unit and provides one or more control signals to the stack renaming unit and coordinates the operation of the stack renaming unit within the stack apparatus.

Abstract: A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the first waiting contender, and the other waiting contenders. The first waiting contender is made probabilistically more likely to obtain the lock by having it spin faster than the other waiting contenders. Because the other waiting contenders spin more slowly, the first waiting contender is more likely to be able to observe the free lock and acquire it before the other waiting contenders notice that it is free. The first of the other waiting contenders that determines that the previous first waiting contender has acquired the lock is promoted to be the new first waiting contender and begins spinning fast. Because only the first waiting contender is spinning fast on the lock, it is probable that only the first waiting contender will attempt to acquire the lock when it becomes available.

Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.

Abstract: A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

Abstract: A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously. The cache includes a first non-blocking cache receiving data access requests from a device in a processor, and a first miss queue storing entries corresponding to data access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided and receives data access requests from the first miss queue, and a second miss queue stores entries corresponding to data access requests not serviced by the second non-blocking cache. A first arbiter arbitrates between two or more access requests to the first non-blocking cache. A second arbiter can be provided to arbitrate between two or more access requests to the second non-blocking cache.The arbiter is capable of determining if an anticipatory stall signal should be asserted if any of the cache resources, such as a queuing structure, is becoming overloaded.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. The bridge also includes a memory subsystem and a bridge control mechanism. The bridge control mechanism is operable to monitor operation of the first and second processing sets in a combined, lockstep, operating mode and to be responsive to detection of a lockstep error to cause the bridge to be operable in an error mode in which write accesses initiated by the processor sets are buffered in a bridge buffer pending resolution of the error mode. A respective buffer region is provided for each processing set. In an initial error mode, any complete device write accesses initiated by the processing sets are stored in a posted write buffer. Where data is in transit through the bridge on entry to the error mode, the data is diverted to one or more disconnect registers.

Abstract: A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: Apparatus, methods, systems and computer program products are disclosed that provide an efficient mechanism for invoking a programmed operation at the first active use of the OOP object or data structure. The programmed operation can be used to initialize an object-oriented programming (OOP) object or data structure. The first active use of the data structure or OOP object is detected because the initial access mechanism is constrained to cause a misaligned memory access fault (trap) by attempting a non-byte access-mode memory access to an odd byte address. As the fault is processed, the access mechanism is converted so that the initial and subsequent non-byte access-mode memory accesses will succeed. In addition, the OOP object or data structure is initialized. Then the initial access attempt is repeated on the just initialized OOP object or data structure using the converted access mechanism.

Abstract: A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first and second miss queues have an indicator associable with each of said entries in the respective miss queues indicating that the entry is a primary reference to data located at the address associated with said entry. If a subsequent instruction generates a cache miss accessing data associated with an entry in a miss queue, the subsequent miss is merged with the appropriate entry in the miss queue and serviced when the primary reference is serviced.

Abstract: One embodiment of the present invention provides a method and an apparatus that ensures proper semantics for operations when operations are restarted on a secondary server in the event of a failure of a primary server. This embodiment keeps a record on the secondary server of which operation currently has exclusive access to a shared resource. The method operates by receiving a message from the primary server indicating that a first operation on the primary server has acquired exclusive access to the shared resource. In response to this message, the system updates state information, at the secondary server, to indicate that the first operation has exclusive access to the shared resource and that any prior operations have completed their exclusive accesses to the shared resource. Upon receiving notification that the primary server has failed, the secondary server is configured to act as a new primary server.

Abstract: A file disaster recovery system that employs geographical replication of data from a local site to remote site in a such a manner that file requests from clients of the local site can be handled by a file server on the remote site following a failover from the local site to the remote site. Geographical data replication software running on a local server checkpoints to a log in local stable storage all information on file operations that change the file state of the local file system. According to a selected mode, the local geographical data replication software flushes information in the log pertaining to the file operations since the last flush to the remote site. At the remote site, compatible remote geographical data replication software running on a remote file server receives the flushed log and replicates in sequence order the file operations represented in the flushed log. The results of the operations are stored on remote stable storage. The local and remote servers can be clusters or single servers.

Abstract: The selector circuit rapidly steers an event from a single input to one of two outputs depending on the binary value of a data signal controlling the selector, where events are received at an event input. A selection value, placed at a control input causes the selector circuit to steer the event to one of the outputs. For each change of value at the event input, one or the other of the outputs will change. Which output changes is determined by the selection value applied to the control input. The selector circuit uses variable or dynamic capacitances at the outputs to control which one of the outputs changes in response to an input event. Each node of the selector circuit includes a true line and a complement line. Pass gates are used to either couple the true lines of the outputs together or to couple the true line of each output and the complement line of the other output.

Abstract: A central site such as an Internet Service Provider (ISP) monitors information requests incoming from devices on a network such as the Internet. If the incoming information indicates that the services of a remote, off-line computer is required, the ISP signals the off-line computer via an out-of-band signal. In response to the signal, the off-line computer connects to the Internet through the ISP in its normal manner, and subsequently responds to the devices.

Abstract: An apparatus for tracking pipeline resources of a processor involves fetching selected ones of the coded instructions and marking the fetched instructions with instruction metadata. The instruction metadata indicates a number of pipeline resources required by each instruction. The marked instructions are issued from the fetch unit and, using the instruction metadata, a count of a number of resources committed to issued instructions in the execution pipelines is maintained. When it is determined that the number of resources committed to issued instructions exceeds a preselected maximum and instructions are prevented from issuing from the fetch unit. As each instruction is retired, the instruction metadata is used to determine a number of resources released by retirement of the issued instruction.

Abstract: A refrigeration system for a disk drive storage is provided. The refrigeration system employs pairs of thin conducting plates, each pair of which is placed so as to sandwich a disk drive. The refrigeration system conducts heat generated from the disk drives via the thin conducting plates, heat pipes coupled to the thin conducting plates, a back plate and a chilled manifold. The heat is further removed as a refrigerant travels through to a compressor and then to a condenser, both of which are connected to the chilled manifold. In this way, the disk drive storage is able to increase its capacity from a bank of twelve disk drives to fourteen disk drives for a 1 inch disk drive storage and from eight disk drives to nine disk drives for a 1.6 inch disk drive storage system, thereby realizing an increased density system without sacrificing a low operating temperature.

Abstract: The present invention provides a voice user interface with personality. In one embodiment, a method includes executing a voice user interface, and controlling the voice user interface to provide the voice user interface with a personality. The method includes selecting a prompt based on various context situations, such as a previously selected prompt and the user's experience with using the voice user interface.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A method and apparatus is disclosed for providing a secure wireless communication link between a mobile nomadic device and a base computing unit. A mobile sends a host certificate (Cert.sub.-- Mobile) to the base along with a randomly chosen challenge value (CH1) and a list of supported shared key algorithms ("SKCS"). The base determines if the Cert.sub.-- Mobile is valid. If the Cert.sub.-- Mobile is not valid, then the base unit rejects the connection attempt. The base then sends a Cert.sub.-- Base, random number (RN1) encrypted in mobile's public key and an identifier for the chosen SKCS to the mobile. The base saves the RN1 value and adds the CH1 value and the chosen SKCS to messages sent to the base. The mobile unit then validates the Cert.sub.-- Base, and if the certificate is valid, the mobile verifies under the public key of the base (Pub.sub.-- Base) the signature on the message.