Abstract: Various embodiments of mechanisms for bridging data representation language messaging based distributed computing environments to foreign environments are described. A device proxy may implement a device protocol and a distributed computing environment protocol to bridge devices into the distributed computing environment. A client proxy is described that implements the distributed computing environment protocol on behalf of a foreign client such as a browser. A service proxy is described that implements the distributed computing environment protocol on behalf of a foreign service. A transport proxy is described that routes data representation language messages between two different message transports. A distributed computing environment client proxy may allow distributed computing environment clients to access Remote Method Invocation (RMI)-based environment services. An RMI-based environment client proxy may allow RMI-based environment clients to access distributed computing environment services.

Abstract: An estimate of the throughput of a multi-threaded processor based on measured miss rates of a cache memory associated with the processor is adjusted to account for cache miss processing delays due to memory bus access contention. In particular, the throughput calculated from the cache memory miss rates is initially calculated assuming that a memory bus between the cache memory and main memory has infinite bandwidth, this throughput estimate is used to estimate a request cycle time between memory access attempts for a typical thread. The request cycle time, in turn, is used to determine a memory bus access delay that is then used to adjust the initial processor throughput estimate. The adjusted estimate can be used for thread scheduling in a multiprocessor system.

Abstract: A dynamic prediction is made whether a load instruction will miss a cache. Data is prefetched for the load instruction when a cache miss is predicted. Thus, the prefetch is only performed if a trigger event correlated with a cache miss for that load instruction is detected. This selective execution of the prefetches for a particular load instruction improves processor utilization and performance.

Abstract: One embodiment of the present invention provides a system that facilitates optimizing computer program performance by using steered execution. The system operates by first receiving source code for a computer program, and then compiling a portion of this source code with a first set of optimizations to generate a first compiled portion. The system also compiles the same portion of the source code with a second set of optimizations to generate a second compiled portion. Remaining source code is compiled to generate a third compiled portion. Additionally, a rule is generated for selecting between the first compiled portion and the second compiled portion. Finally, the first compiled portion, the second compiled portion, the third compiled portion, and the rule are combined into an executable output file.

Abstract: Methods and systems for protecting object identity in an object-oriented programming language. An object from a class for protecting object identity is instantiated in memory. The object includes a first method that determines whether two object values are equal, and a second method that overrides an identity method associated with a superclass of the object by invoking the first method, the identity method for determining the identity of two objects. The object is immediately locked in response to the instantiating, so that the identity of the locked object is protected from threads that attempt to synchronize on the locked object.

Abstract: A method for processing a chain of packets involving obtaining the chain of packets from a network, obtaining destination information from a first packet in the chain of packets, determining whether destination information of the first packet matches destination information of a second packet in the chain of packets, aggregating the first packet and the second packet to obtain an aggregated chain of packets, if destination information of the second packet matches the destination information of the first packet, hashing destination information to obtain a hash value, and forwarding the aggregated chain of packets to at least one client using the hash value.

Abstract: One embodiment of the present invention provides a system that supports low-latency session-mobility for an ultra-thin-client. During system operation, an ultra-thin-client sends a location-identifier to a Connection Assignment Server (CAS), which facilitates communication with a user-interface (UI) server, wherein the location-identifier specifies the current location of the ultra-thin-client. Next, the ultra-thin-client receives the address of a local UI-server from the CAS, wherein the CAS selects the local UI-server based on the location-identifier. The ultra-thin-client then sends a user-session identifier to the local UI-server. This allows the local UI-server to retrieve a user-session-image for a user-session from a user-session-image repository. Note that, before moving to the current location, the ultra-thin-client was previously communicating with a remote UI-server, which stored the user-session-image in the user-session-image repository.

Abstract: In some embodiments, a computer system comprises a cache configured to cache data. The computer system is configured to monitor the cache and data that is potentially cacheable in the cache to accumulate a plurality of statistics useable to identify which of a plurality of data lifecycle patterns apply to the data. The computer system is also configured to modify a cache configuration of the cache dependent on which of the plurality of data lifecycle patterns apply to the data.

Abstract: In one embodiment, a processor comprises a plurality of processor cores and an interconnect to which the plurality of processor cores are coupled. Each of the plurality of processor cores comprises at least one translation lookaside buffer (TLB). A first processor core is configured to broadcast a demap command on the interconnect responsive to executing a demap operation. The demap command identifies one or more translations to be invalidated in the TLBs, and remaining processor cores are configured to invalidate the translations in the respective TLBs. The remaining processor cores transmit a response to the first processor core, and the first processor core is configured to delay continued processing subsequent to the demap operation until the responses are received from each of the remaining processor cores.

Abstract: The present application describes techniques for determining maximum acceptable modeled load latency (e.g., a model number of clock cycles required between the time a load issues and the time its use can issue) for instruction scheduling which uses less compile time, on the order of log2 (Maximum load latency—Minimum load latency). Typically, during instruction scheduling, register pressure is monotonically non-decreasing with respect to the scheduled load latency. Therefore, in some embodiments, a hierarchical search method is used to determine the acceptable schedule with the largest modeled load latency. According to an embodiment, a binary search is employed which reduces the compile time required to determine maximum load latency for which registers can be assigned.

Abstract: A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.

Abstract: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

Abstract: A method for tracing of instructions executed by a processor is provided which includes providing a type of instruction to be traced and tracing at least one instruction corresponding to the type of instruction. The method further includes storing data without stopping from the tracing into a memory until the memory is full.

Abstract: One embodiment of the present invention provides a system that asynchronously controls the sending of data items from a sender to a receiver. The system includes a data path between the sender and the receiver, a first control path between the sender and the receiver, and a second control path between the sender and the receiver. The first control path and the second control path alternately control the asynchronous transmission of consecutive data items on the data path between the sender and the receiver.

Abstract: A method and apparatus for determining whether a TCP packet lands in-zone or out-of-zone of a TCP sequence space. An anchor representing the TCP sequence number of the last TCP data byte, plus one, is updated each time a TCP data packet is received. When a new TCP packet is received, the most significant bit, bit [31], is extracted from the anchor. A two-bit value is formed by adding 1 to the extracted bit. This two-bit value is pre-pended to bits [30:0] of the anchor, as bits [32:31], to produce a 33-bit test value. Then, the sequence number of the last TCP byte of the received packet is then compared to the anchor and the test value. If the sequence number is greater than or equal to the anchor, and less than the test value, the packet lands in-zone and may be processed normally.

Abstract: A mapping engine, capable of receiving descriptions of manageable software objects in a first language, for generating management information in a second language. The mapping engine is further capable of generating a set of mapping metadata, corresponding to the management information as generated. The mapping engine may be further responsive to user input. In another embodiment, a metadata compiler is provided, capable of receiving management information in a second language, and corresponding mapping metadata, for generating compiled metadata, applicable when using said management information in a first language. The metadata compiler may be used in connection with the above first aspect.

Abstract: A method for managing memory in a multi-tasking virtual machine, involving suspending a first task for garbage collection of a plurality of concurrently executing tasks, promoting at least one object associated with the first task to a old generation using a gap buffer to obtain a promoted object, wherein the gap buffer stores a gap created by objects directly allocated by at least one of the plurality of concurrently executing tasks, locating the promoted object using the gap buffer, traversing the promoted object to determine whether a first referenced object exist, and promoting the first referenced object using the gap buffer, if the first referenced object exists.

Abstract: A system is provided for detecting when a temperature of a multiprocessor chip approaches an established threshold temperature indicating an imminent overheat condition. When the threshold temperature is reached, a number of active threads are idled in order to remove their contribution from the overall power consumption of the multiprocessor chip. Idling of the threads serves to prevent the multiprocessor chip from reaching the overheat condition. Once the temperature of the multiprocessor chip drops to an acceptable level, execution of the previously idled threads is resumed. Detection of the imminent overheat condition and corresponding idling of the threads to avoid reaching the overheat condition is conducted by hardware to ensure timely reduction of the multiprocessor chip temperature.

Abstract: A method for caching in a tracing framework, including firing a probe associated with a thread, evaluating a first predicate of the probe, caching the first predicate in a predicate cache associated with the thread, based on the evaluating of the first predicate and cacheability of the first predicate, and transferring control to the thread, based on the caching.

Abstract: An improved mechanism for tracking the execution progress of a task is disclosed. In one implementation, the execution progress of a parent task and one or more child tasks is monitored. The parent task spawns the one or more child tasks, and the child tasks execute concurrently with the parent task. In addition to monitoring the execution progress of the tasks, an overall execution progress value is determined for the parent task. In one implementation, the overall execution progress value is determined based, at least partially, upon the execution progress of the parent task and the execution progress of at least one of the child tasks. By taking the execution progress of the child tasks into account, the overall execution progress value reflects not just the progress made by the parent task itself but also the progress made by the child tasks that it spawned.