Abstract: One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted. During this speculative execution, registers are updated by checkpointing an old value of the register, if the register has not already been checkpointed, and then updating the architectural state of the register with the new value. In this way, only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.

Abstract: An apparatus for cooling a computer system includes a fan for flowing an air to a first assembly and a second assembly, a first filter for filtering an air to a first assembly, and a second filter for filtering an air to a second assembly. The first filter is disposed at a side of the first assembly and the second filter is disposed on an opening of a wall which separates the first assembly and the second assembly.

Abstract: A method for securing a commercial grid network over non-trusted routes involves receiving, by an administrative node in the commercial grid network, a lease request from a client to lease one of multiple resource nodes in the commercial grid network, wherein the client is separated from the resource node by a non-trusted route. The method further involves transmitting, by the administrative node, a network security key associated with the client to the resource node, storing, by the resource node, the network security key in a network security key repository specific to the resource node, establishing, by the resource node, a secure network tunnel over the non-trusted route using the network security key, transmitting a network packet securely between the client and the resource node over the secure network tunnel, and destroying, by the resource node, the secure network tunnel when a lease term associated with the client and the resource node expires.

Abstract: A method for visualizing web service interactions includes invoking a remote operation that causes a plurality of messages to be sent between two components in a connected system. The method further includes visually identifying a swim lane for each of the two components in a graphical display. For each message, a vector is plotted in the graphical display, where the vector extends from the swim lane of the message sender to the swim lane of the message recipient. The relative position of each vector depends on the time when the message was sent. A machine readable medium and an integrated development environment for representing asynchronous web service execution are also provided.

Abstract: A system and method are provided for controlling the computing bandwidth and resources provided to external entities based on subscription levels associated with those external entities. Higher subscription levels provide greater resource allocation. Accounting is accomplished by tracking bandwidth allocated and used over given periods of time.

Abstract: One embodiment of the present invention provides a system that can test an interface between a TCP (Transmission Control Protocol) Offload Engine (TOE) and an OS (Operating System) that has a TCP software stack. Note that the TOE is a specialized integrated circuit which allows TCP-related computations to be offloaded from the processor that executes the OS. During operation, the system receives a request from the OS to perform a TCP-related computation on the TOE, wherein the TCP-related computation is associated with a portion of the TCP software stack. The system then performs the TCP-related computation by executing the portion of the TCP software stack on a processor, which can either be the same as the one that is executing the OS, or it can be a different processor. Note that performing the TCP-related computation on a processor, instead of the TOE, allows the interface between the TOE and the OS to be tested without requiring an actual TOE chip.

Abstract: An approach for freeing memory based upon its relocatable or non-relocatable property is provided. In one embodiment, drivers and other processes that do not provide callback methods or similar capability to route DMA requests to the correct physical address are identified and all memory allocations made by the driver or other process are made from the appropriate region.

Abstract: Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the targeted read operations facilitates aggressive speculative execution without significant performance impact and without hardware support. A software value predictor issues prefetches for targeted read operations during speculative execution, and utilizes values from these prefetches during subsequent speculative execution, since the earlier prefectches should have completed, to update a software value prediction structure(s). Such a software based value prediction technique allows for aggressive speculative execution without the overhead of a hardware value predictor.

Abstract: An apparatus and method are provided for simulating a target storage configuration for a computer system. In particular, a storage command is received from an application running on the computer system into a storage protocol stack on the computer system. The storage protocol stack is part of an operating system of the computer system and runs in kernel mode. The storage command is intercepted within the storage protocol stack by a kernel simulator module incorporated into the storage protocol stack. The intercepted storage command is forwarded from the kernel simulator module to a userland simulator module running in user mode. The userland simulator module generates a response to the storage command, where the response emulates the behavior of the target storage configuration. The response is then sent from the userland simulator module to the kernel simulator module, to be returned from the kernel simulator module to the application via the storage protocol stack.

Abstract: A system and method for providing exceptional flow control in protected code through memory layers. Code is generated. The generated code includes a sequence of normal operations and is subject to protection against copying during execution of the generated code. The generated code is instantiated as a master process into a master layer in a memory space. The master process is cloned by instantiating a copy of the master process as a child layer in the memory space. Execution points within the generated code are identified. A copy of at least a portion of the generated code containing each execution point as an exception layer is instantiated in the memory space. The generated code in the exception layer is patched at each identified execution point with operations exceptional to the normal operations sequence and which are performed upon a triggering of each execution point during execution of the generated code.

Abstract: A computer system comprising a main memory and a processor die coupled to the main memory by a first bus. The processor die includes a processor core coupled to a first cache memory and multiple base and bounds registers (BBRS). Each of BBRs have a base virtual address field, an ending virtual address field and a base physical address field. The first cache memory has a table lookaside buffer (TLB) entry stored therein.

Abstract: A method and apparatus for stopping the internal clock of a microprocessor synchronously with the execution of an instruction is provided. A stop instruction is placed in a sequence of instructions to be executed by the microprocessor. The execution of the stop execution may store a stop value into a stop register of the microprocessor. Clock stop logic detects when the stop value has been stored into the stop register. The clock stop logic instructs a clock generation component, of the microprocessor, to cease generation of an internal clock signal, thereby preventing the microprocessor from changing state. As further instructions are not executed by the microprocessor, the state of the microprocessor reflects the execution of the instruction immediately prior to the stop instruction. The processing state of the microprocessor may be obtained for use in debugging the design of the microprocessor or the instructions executed thereby.

Abstract: One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and uses state information that is specific to the process to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.

Abstract: A network trace utility is provided. The network trace utility receives and copies packets in a secure session of (at least) two-way network communication between a client and a server. The network trace utility receives an administrator password, and uses a hash of the administrator password to decrypt the first session key. The network trace utility then decrypts one or more additional session keys, each one using the preceding session key. Then, the network trace utility decrypts the machine key using one of the session keys. A hash of the machine key is used to decrypt additional packets in the secure session. The network trace utility enables the contents of one or more additional packets in the secure session to be displayed to the user.

Abstract: In a switch system L groups of the line switch elements are connectable to cables that include L links such that each of the L links within a cable connect to a switch element of a respective one of the L groups. Fabric switch elements are connected such that a fabric switch element is connected to the line switch elements of one of the group of line switch elements.

Abstract: A computer implemented method and system for filtering incoming electronic messages based on user objectives is disclosed. For example, automated assistance can be provided in realizing a user objective of filtering electronic mail (e-mail) messages associated with a “conversation” thread. The electronic message filtering system can receive an e-mail message, examine attributes or characteristics of the e-mail message, determine if a rule has been established for messages with the characteristics of the incoming message, and if there has been a rule set up, automatically implement an action in accordance with the rule. For example, when electronic messages with particular information in the header (e.g., a particular subject) are received, the messages are automatically moved to a designated trash folder. Additionally, finer granularity of message management can be achieved (e.g., an action is automatically implemented to display a message from a particular sender at the top of a list).

Abstract: One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code on a non-speculative mode. Upon encountering a stall condition, the system checkpoints the state of the processor and executes the code in a speculative mode from the point of the stall. As the processor commences execution in speculative mode, it stores copies of instructions as they are issued into a recovery queue. When the stall condition is ultimately resolved, execution in non-speculative mode is recommenced and the execution units are initially loaded with instructions from the recovery queue, thereby avoiding the delay involved in waiting for instructions to propagate through the fetch and the decode stages of the pipeline. At the same time, the processor begins fetching subsequent instructions following the last instruction in the recovery queue.

Abstract: A method for caching a block, which includes receiving a request to store the block in a cache and determining whether the cache is able to expand. If the cache is not able to expand, then determining whether evictable blocks are present in the cache and, if evictable blocks are present in the cache determining whether a total size of the evictable blocks is greater than or equal to a size of the block, evicting a sufficient number of the evictable blocks from the cache and storing the block in the cache, if the total size of the evictable blocks is greater than or equal to the size of the block, and activating a cache throttle, if the total size of the evictable blocks is less than the size of the block.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Abstract: A system and method for dynamically calculating margin for a set of computer resources (e.g., processors, disk storage, memory, communications). The headroom of a set of resources is equal to the total capacity of the resources minus a margin. Margin is a portion of the total capacity not to be used, so as to allow for acceptable response times. An initial margin may be selected using a graph plotting total resource utilization level percentage against response time. For a desired or acceptable response time factor, the initial margin is selected as 100% minus the utilization percentage that yields the selected response time factor. Then, as the workload is run, data are collected showing response times for different load levels. A modified curve is generated (e.g., using standard regression) and a new margin selected from that curve.