Patents Assigned to SunEdison Semiconductor Limited
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Publication number: 20170256439Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.Type: ApplicationFiled: July 28, 2016Publication date: September 7, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
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Publication number: 20170234960Abstract: A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.Type: ApplicationFiled: September 16, 2015Publication date: August 17, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Igor Rapoport, Robert James Crepin, Patrick Alan Taylor
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Patent number: 9727045Abstract: A method and system for computerized coordination of multiple operations to be performed by components of machines are provided. The computer system includes a memory device for storing data and a computer-controlled machine that includes a processor in communication with the memory device wherein the processor is programmed to read a recipe file from the memory device, the recipe file including operating parameter values for controlling the operation of the machine, extract a name of a meta-recipe file from the recipe file, the meta-recipe file including a first portion including parameter properties of operating parameter values used by the meta-recipe file, receive values for the meta-recipe having the parameter properties specified in the first portion, and operate the machine using code from a second portion of the meta-recipe and the received values.Type: GrantFiled: December 20, 2013Date of Patent: August 8, 2017Assignee: SUNEDISON SEMICONDUCTOR LIMITED (UEN201334164H)Inventors: Benno Orschel, Mike Wolfram
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Publication number: 20170178890Abstract: Methods for polishing semiconductor substrates are disclosed. The finish polishing sequence is adjusted based on a measured edge roll-off of an analyzed substrate.Type: ApplicationFiled: December 21, 2016Publication date: June 22, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Alex Chu, Hsin-Yi Chi, Francis Hung, Jones Yang, H.J. Chiu, J.W. Lu
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Patent number: 9665931Abstract: Methods and systems for use in detecting an air pocket in a single crystal material are described. One example method includes providing a matrix including a plurality of data units, the plurality of data units including image data related to a region of interest of the single crystal material; determining, by a processor, a difference between data units of the matrix and a corresponding data unit of the matrix, wherein the corresponding data unit is defined by a first operation of the matrix; calculating, by the processor, a first index value based on the differences of the corresponding data units; and identifying an air pocket within the single crystal material based on the first index value and a predetermined threshold.Type: GrantFiled: December 12, 2012Date of Patent: May 30, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventor: John F. Valley
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Patent number: 9634689Abstract: A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set.Type: GrantFiled: August 20, 2014Date of Patent: April 25, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventor: Markus Jan Peter Siegert
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Patent number: 9601395Abstract: In one aspect, a method of predicting warp in a plurality of wafers after an epitaxial layer deposition process is provided. The method includes receiving, by a processor, a measured resistivity of a first wafer of the plurality of wafers, receiving, by the processor, a measured shape of the first wafer after at least one of a grinding process and an etching process, and calculating, using the processor, a change in wafer shape during the epitaxial layer deposition process. The method further includes superposing, using the processor, the calculated shape change onto the measured shape of the first wafer to determine a post-epitaxial wafer shape and calculating, using the processor, a post-epitaxial warp value based on the determined post-epitaxial wafer shape.Type: GrantFiled: December 28, 2012Date of Patent: March 21, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Sumeet S. Bhagavat, Roland R. Vandamme
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Patent number: 9583364Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.Type: GrantFiled: December 27, 2013Date of Patent: February 28, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
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Patent number: 9583363Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.Type: GrantFiled: December 27, 2013Date of Patent: February 28, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
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Publication number: 20170053826Abstract: Polishing slurries for polishing semiconductor substrates are disclosed. The polishing slurry may include first and second sets of colloidal silica particles with the second set having a silica content greater than the first set.Type: ApplicationFiled: July 28, 2016Publication date: February 23, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Hui Wang, Vandan Tanna, Tracy Michelle Ragan, James Raymond Capstick
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Patent number: 9566687Abstract: A polishing head assembly for single side polishing of silicon wafers is provided. The polishing head assembly includes a polishing head and a cap. The polishing head has a recess along a bottom portion, the recess having a recessed surface. The cap is positioned within the recess, and has an annular wall and a floor extending across the annular wall. The floor is spaced from the recessed surface to form a chamber therebetween. The chamber is configured to be pressurized for deflecting the floor. The annular wall is attached to the polishing head with an adhesive.Type: GrantFiled: October 13, 2014Date of Patent: February 14, 2017Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Peter Albrecht, Sumeet Bhagavat, Alex Chu, Ichiro Yoshimura, Yunbiao Xin, Roland Vandamme
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Publication number: 20170025307Abstract: Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.Type: ApplicationFiled: January 9, 2015Publication date: January 26, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Michael J. Ries, Jeffrey Louis Libbert, Charles R. Lottes
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Publication number: 20170025306Abstract: Methods for preparing silicon-on-insulator structures and related intermediate structures are disclosed. In some embodiments, a single crystal silicon seed crystal is bonded to an amorphous silicon layer disposed on a substrate and the amorphous layer is crystallized to form a monocrystalline silicon layer.Type: ApplicationFiled: June 24, 2016Publication date: January 26, 2017Applicant: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Gang Wang, Jeffrey L. Libbert, Qingmin Liu, Alex Usenko, Shawn George Thomas
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Patent number: 9459935Abstract: A computing device is configured to execute a first instance of a single-threaded script engine in a first thread associated with a first execution context, wherein the first instance of the single-threaded script engine accesses at least one shared script object through a first reference counted script base value object. The computing device is also configured to concurrently execute a second instance of the single-threaded script engine in a second thread_associated with a second execution context, wherein the second instance of the single-threaded script engine accesses the at least one shared script object through a second reference counted script base value object. The script engine does not switch between the execution contexts.Type: GrantFiled: December 27, 2013Date of Patent: October 4, 2016Assignee: SunEdison Semiconductor LimitedInventor: Benno Orschel
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Patent number: 9401271Abstract: Apparatus and methods for wafer processes such as etching and chemical vapor deposition processes are disclosed. In some embodiments, the apparatus includes a susceptor and a ring disposed beneath the susceptor to influence a thickness of the deposited epitaxial layer.Type: GrantFiled: March 15, 2013Date of Patent: July 26, 2016Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: John Allen Pitney, Manabu Hamano
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Patent number: 9384540Abstract: A method for measuring phase shift to detect irregularities of a surface is described. Additionally, a system for measuring phase shift to detect irregularities of a surface is provided. Further, a non-transitory computer-readable storage medium having computer-executable instructions embodied thereon is described. The computer-executable instructions are for measuring phase shift to detect irregularities of a surface.Type: GrantFiled: December 3, 2013Date of Patent: July 5, 2016Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventor: Benno Orschel
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Patent number: 9355842Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.Type: GrantFiled: January 29, 2015Date of Patent: May 31, 2016Assignees: SunEdison Semiconductor Limited (UEN201334164H), Kansas State University Research FoundationInventors: Michael R. Seacrist, Vikas Berry, Phong Tuan Nguyen
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Patent number: 9343533Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.Type: GrantFiled: October 8, 2014Date of Patent: May 17, 2016Assignees: SunEdison Semiconductor Limited (UEN201334164H), Kansas State University Research FoundationInventors: Michael R. Seacrist, Vikas Berry
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Patent number: 9343379Abstract: This invention generally relates to a process for detecting grown-in-defects in a semiconductor silicon substrate. The process includes contacting a surface of the semiconductor silicon substrate with a gaseous acid in a reducing atmosphere at a temperature and duration sufficient to grow grown-in -defects disposed in the semiconductor silicon substrate to a size capable of being detected by an optical detection device.Type: GrantFiled: October 4, 2011Date of Patent: May 17, 2016Assignee: SunEdison Semiconductor LimitedInventors: Jeffrey L. Libbert, Lu Fei
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Patent number: 9330014Abstract: A method and data-logging system are provided. The system includes a map-ahead thread configured to acquire blocks of private memory for storing data to be logged, the blocks of private memory being twice as large as the file page size, a master thread configured to write data to the blocks of private memory, in real-time and in full resolution, the data acquired during operation of a machine generating the data and written to the blocks of private memory in real-time, the machine including a controller including a processor communicatively coupled to a memory having processor instructions therein, and a write-behind thread configured to acquire pages of memory that are mapped to pages in a file, copy the data from the blocks of private memory to the acquired file-mapped blocks of memory.Type: GrantFiled: December 20, 2013Date of Patent: May 3, 2016Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Benno Orschel, Mike Wolfram