Patents Assigned to Synopsys, Inc.
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Publication number: 20050123841Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.Type: ApplicationFiled: January 13, 2005Publication date: June 9, 2005Applicant: Synopsys, Inc.Inventor: Christophe Pierrat
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Patent number: 6904587Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.Type: GrantFiled: December 20, 2002Date of Patent: June 7, 2005Assignee: Synopsys, Inc.Inventors: Chi-Ming Tsai, Chin-Hsen Lin, Yao-Ting Wang
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Patent number: 6901471Abstract: A system wherein a signal over a Universal Serial Bus (USB) interface is received by a receiver component. A mixed signal block utilizes a mixed signal interface to transmit the signal to a processor block.Type: GrantFiled: March 1, 2001Date of Patent: May 31, 2005Assignee: Synopsys, Inc.Inventor: Ravikumar Govindaraman
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Patent number: 6880135Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.Type: GrantFiled: November 7, 2001Date of Patent: April 12, 2005Assignee: Synopsys, Inc.Inventors: Fang-Cheng Chang, Christophe Pierrat, J. Tracy Weed
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Patent number: 6874132Abstract: Embodiments of the present invention relate to a computer-controlled method for extracting cell parasitic characteristics for netlist back-annotation in a circuit that comprises a row and column array of repeated cells. The method comprises the steps of generating parasitic and connection data for a row and a column of said cells in the arrayed circuit, duplicating the generated parasitic data for an additional row and an additional column in the arrayed circuit; synthesizing connection data for the additional row from a connected cell in that additional row; synthesizing connection data for the additional column from a connected cell in that additional column, and making the generated parasitic data and the synthesized connection data available for subsequent back-annotation of the netlist.Type: GrantFiled: September 11, 2002Date of Patent: March 29, 2005Assignee: Synopsys, Inc.Inventor: Achyutram Bhamidipaty
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Patent number: 6873720Abstract: A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.Type: GrantFiled: March 20, 2001Date of Patent: March 29, 2005Assignee: Synopsys, Inc.Inventors: Lynn Cai, Linard Karklin, Linyong Pang
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Patent number: 6866971Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.Type: GrantFiled: November 14, 2002Date of Patent: March 15, 2005Assignee: Synopsys, Inc.Inventor: Christophe Pierrat
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Patent number: 6865525Abstract: A method and apparatus for simulating a circuit is described. In one embodiment, the method comprises representing a plurality of identical components in a reduced form as a circuit having a single instance of the identical component with encoding for each input of the single instance to represent corresponding inputs to all of the plurality of identical components and decoding for each output port of the single instance to create output ports for the outputs associated with all of the plurality of identical components and symbolically simulating the reduced form of the circuit with simulation results being the same as results of symbolically simulating the plurality of identical components.Type: GrantFiled: January 30, 2001Date of Patent: March 8, 2005Assignee: Synopsys, Inc.Inventor: John Xiaoxiong Zhong
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Patent number: 6861204Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.Type: GrantFiled: March 26, 2004Date of Patent: March 1, 2005Assignee: Synopsys, Inc.Inventors: Michel Luc Côté, Christophe Pierrat
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Patent number: 6859914Abstract: A method of identifying semiconductor design candidates from a population of semiconductor technology designs leverages specialized operators which are smooth in the sense that the operators are capable of producing small changes in the performance or behaviour when applied to a design to modify it. The method includes determining a smooth operator for effecting incremental structural change to a semiconductor technology design when the smooth operator is applied to the semiconductor technology design and then applying the smooth operator to at least one semiconductor technology design in the population to determine an updated population. The semiconductor technology designs in the updated population are evaluated to identify a preferred semiconductor technology design candidate. If the stopping condition is satisfied then the search terminates otherwise the steps are repeated.Type: GrantFiled: August 27, 2002Date of Patent: February 22, 2005Assignee: Synopsys, Inc.Inventor: Trent Lorne McConaghy
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Patent number: 6853035Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAW using such elements is disclosed Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.Type: GrantFiled: April 26, 2004Date of Patent: February 8, 2005Assignee: Synopsys, Inc.Inventor: Tsu-Jae King
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Patent number: 6851099Abstract: The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Initial placement and placement refinement may be performed hierarchically using topocluster trees. A topocluster tree may be used to drive initial placement. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM). In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics-delay, area, congestion, power, etc.Type: GrantFiled: February 23, 2000Date of Patent: February 1, 2005Assignee: Synopsys, Inc.Inventors: Majid Sarrafzadeh, Salil R. Raje
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Patent number: 6848085Abstract: A computer aided hardware design system for enabling design of an actual hardware implementation for a digital circuit using a high-level algorithmic programming language. The system converts an algorithmic representation for a hardware design initially created in the high-level programming language, such as ANSI C, to a hardware design implementation, such as an FPGA or other programmable logic or an ASIC. The C-type program representative of the hardware design is compiled into a register transfer level (RTL) hardware description language (HDL) that can be synthesized into a gate-level hardware representation. The system additionally enables simulation of the HDL design to verify design functionality. Finally, various physical design tools can be utilized to produce an actual hardware implementation. The system also permits the use of other non-C-type high-level programming languages by first translating to a C-type program.Type: GrantFiled: April 30, 2001Date of Patent: January 25, 2005Assignee: Synopsys, Inc.Inventors: Yuri V. Panchul, Donald A. Soderman, Denis R. Coleman
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Patent number: 6816938Abstract: A system on-chip interface device includes a plurality of cores comprising core systems a plurality of standard interfaces interfaced to the plurality of cores a system bus, an on-chip bus, a plurality of system interface blocks comprising first and second interfaces, wherein the first interface comprises a standard interface interfaced to at least one core system and the second interface comprises an interface interfaced to the system bus, a system bus bridge comprising first and second system bus interfaces wherein the first system bus interface comprises an interface interfaced to the system bus and the second system bus interface comprises a standard interface, an on-chip bus bridge comprising first and second on-chip bus interfaces wherein the first on-chip bus interface comprises a standard interface interfaced to the system bus bridge and the second on-chip bus interface comprises an interface interfaced to the on-chip bus.Type: GrantFiled: March 27, 2001Date of Patent: November 9, 2004Assignee: Synopsys, Inc.Inventors: Sagar Edara, Amjad Qureshi, Ajit Deora, Ramana Kalapatapu
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Patent number: 6810506Abstract: A computer implemented method of producing a reduced order model of an electronic circuit to model the connection of two or more circuits. Arnoldi reduced order models for nodes of circuits to be interconnected may be computed. A set of modified nodal analysis matrices for the combination of the two circuits may be constructed. A rank one update may be applied to the modified set of nodal analysis matrices to produce a reduced order model of the combined electronic circuits. In this novel manner, a reduced order model for a combination of circuits may be produced from the individual reduced order models of the individual circuits without the need to recompute the reduced order models of the original circuits, and without the need of the original parasitic network models. The resulting reduced order model may be used in a variety ways consistent with well known uses of such matrices within the field of electronic design automation.Type: GrantFiled: May 20, 2002Date of Patent: October 26, 2004Assignee: Synopsys, Inc.Inventor: Harold J. Levy
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Patent number: 6810482Abstract: The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates.Type: GrantFiled: January 26, 2001Date of Patent: October 26, 2004Assignee: Synopsys, Inc.Inventors: Vikram Saxena, Renu Mehra
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Patent number: 6810373Abstract: A method and apparatus for modeling using a hardware-software software co-verification environment is provided. An instruction set simulator is coupled to a simulator circuit to determine if the hardware design is correct. Specifically, the instruction set simulator acts as a “master” to the simulator circuit, thus providing a faster simulation environment. The simulator circuit contains a bus functional model, a hardware model, transfer memory, and the hardware design to be tested. The hardware model is designed to emulate a micro-controller. By disabling a processor within the hardware model, the speed of the simulation is restricted only by the speed of the instruction set simulator or the hardware design. Furthermore, the hardware design may be uncoupled from the simulator circuit in order to initialize the operating system.Type: GrantFiled: August 11, 2000Date of Patent: October 26, 2004Assignee: Synopsis, Inc.Inventors: Bruce Harmon, Michael Butts, Gordon Battaile, Kevin Heilman, Levent Caglar, Raju Marchala, Larry Carner, Kamal Varma
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Patent number: 6810483Abstract: A method and system is provided for synchronizing data between an application layer having a first clock speed and a circuit having a second clock speed. The first clock speed generally being faster than the second clock speed. The second clock speed typically being determined by an appropriate standard. Data and a function opcode representative of a computation to be performed on at least a portion of the data, is received at a synchronizing element from the application layer. The synchronizing element may be a first in first out type device. The data and its associated function opcodes are stored by the synchronizing element until transmitted to a circuit in accordance with the second clock speed. A compute logic in the circuit performs a computation on at least a portion of the data based on the associated function opcode. A system is also provided for synchronizing data between an application layer and a logic circuit. The system may be advantageously employed in audio/visual applications.Type: GrantFiled: January 25, 2001Date of Patent: October 26, 2004Assignee: Synopsys, Inc.Inventor: Anuradha Bommaji
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Patent number: 6810389Abstract: A method for providing licenses to client computer systems to allow the client computer systems to use licensed software products includes receiving a request for a feature license for a feature included in a package, filtering the request based on whether the license requires the checkout of a parent license, granting a package license to the client computer system when the client computer system is allowed to receive the package license according to a license policy and denying the package license to the client computer system when the client computer system is not allowed to receive the package license according to the license policy. The request may include checkout data that includes at least one desired feature attribute.Type: GrantFiled: November 8, 2000Date of Patent: October 26, 2004Assignee: Synopsys, Inc.Inventor: Marc A. Meyer
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Patent number: 6810484Abstract: The device and method that receives a signal from a first interface operating at a data rate. An extraction component extracts information from the signal to produce an information signal having a frequency distinct from the data rate of the first interface. A first receive clock component receives a first clock signal that has a frequency equal to a frequency of a second interface. A synchronizer component synchronizes the information signal through utilization of the first clock signal to the frequency of the second interface.Type: GrantFiled: March 1, 2001Date of Patent: October 26, 2004Assignee: Synopsys, Inc.Inventor: Ravikumar Govindaraman