Abstract: A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T.

Abstract: A modeling method to incorporate transparency into black box models using setup time in a circuit timing model. The circuit timing model, comprising a plurality of latches initially represented using black box models, is generated. For each of the plurality of latches, an arrival time is calculated from the latch clock pin to an interface data output pin of the timing model, and the maximum arrival time is determined. For each of the plurality of latches, a setup time is calculated. A setup time is also calculated using the delay time from the interface data input pin to the interface data output pin and the maximum arrival time. The worst-case set up time is selected from these setup times and imposed at the interface data input pin. Satisfaction of the worst-case setup time causes the maximum arrival time to also be satisfied.

Abstract: A computer implemented method for verifying a physical layout of an integrated circuit design for a semiconductor chip. The physical layout is specified in terms of a plurality of layers used to fabricate the chip. Initially, a pre-defined set of rules are stored in memory. These rules are used to specify certain dimensions for properly laying out the physical design of the IC. For each rule, one or more layers applicable to that rule is specified. Instead of reading a rule and then applying that rule to the relevant portions of the physical layout, the present invention reads one or more layers pertaining to the physical layout and then determines all rules applicable to those layers. The layers are then verified against the appropriate rules. Any error conditions are stored for subsequent display to the designer or engineer. By performing a layer based rule checking scheme, the number of read operations required, which reduces the time it takes to perform the verification process.

Abstract: In the design of integrated circuits, a computer controlled method for the rough placement of cells. Initially, a synthesis tool is used to generate a netlist according to HDL, user constraint, and technology data. Thereupon, a cell separation process assigns (x,y) locations to each of the cells. The cell location information is supplied to the synthesis tool, which can then make changes to the netlist thereto. In the present invention, the size of the placement area is allowed be scaled according to the new netlist. Next, the cells are spaced apart according to a spacing algorithm. A partitioning algorithm is then applied to group the cells into a plurality of partitions. A number of iterations of cell separation, synthesis of new netlist, size adjustment (if necessary), spacing, and partitioning are performed until the cells converge. Thereupon, detailed placement and routing processes are used to complete the layout.

Abstract: A method and system for high speed detailed placement of cells within an integrated circuit design. The novel detailed placement system receives a set of cells of an integrated circuit design where the cells have undergone coarse placement. Cells have variable width but the same height (or vice-versa). The cells are each assigned an initial coordinate position, e.g., using floating point precision values. During detailed placement, the cell coordinates are assigned to x-axis and y-axis grid lines. The detailed placement process sorts the cells based on their coordinates along a first axis, e.g., their x-axis coordinates; sort order dictates cell placement order. In one embodiment, sort order preference is given to the wider cells. For a given cell, placement is performed by scanning through the rows of the substrate and selecting the left-most positioned vacant site of each row as a candidate site for placement. A site is vacant if it does not contain a previously placed cell.

Abstract: In a multiport memory semiconductor integrated circuit, an efficient method of testing the memory for faults. The method determines a base address in a multiport memory. A plurality of addresses are scanned within the memory which are at a hamming distance of 1 from the base address, such that at least two memory cells in each column of the multiport memory device are accessed in the scan. This allows the detection of cross port faults, address mismatch faults, and bit shorts due to the fact that the faults are exposed when the two memory cells sharing access columns are accessed with test data. The method functions nominally without requiring any detailed information about the placement and routing structure of the multiport memory device.

Abstract: An efficient, gridless, cost-based coarse router having layer assignment for a computer controlled integrated circuit design. The coarse routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the coarse wire routing process, a number of obstructions are defined. Next, the horizontal and vertical passages between adjacent obstructions, through which wires may be routed, are determined. The costs for possible wire paths connecting a pair of pins are computed based upon wire density histograms associated with the various passages through which the paths traverse. The lowest cost path is then selected. In order to increase the processing speed, a pruning method is employed to minimize the number of possible paths to be considered. In some instances, there may be areas which are overly congested. For overly congested areas, a pseudo obstruction is artificially created by the coarse router.

Abstract: This is a method of quickly computing the power dissipated by a digital circuit using information available at the gate library level. It estimates the short-circuit power by modeling the energy dissipated by the cell per input transition as a function of the transition time or edge rate, and multiplying that value by the number of transitions per second for that input.

Abstract: In the design of digital integrated circuits, it is often desirable to formally verify whether an implementation design is equivalent to a reference design. The present invention facilitates such formal verification by determining “necessary correspondences” between inputs or outputs of the two circuits to be compared for equivalency. Necessary correspondences are so called because while they establish necessary conditions for equivalency to occur, they are not sufficient to determine that equivalency actually exists. Once such necessary correspondences have been determined, algorithms to determine actual equivalency can be more strategically applied. It is often cost-effective (i.e. more efficient), as part of an equivalency-determining circuit design tool, to first apply the teachings of the present invention in order to lessen subsequent application of an equivalency determining method.

Abstract: An efficient iterative, gridless, cost-based router for a computer controlled integrated circuit design. The fine routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the wire routing process, wires are routed between pins of nets. The routing process of the present invention is gridless and utilizes lanes that are defined based on the boundaries of objects. The cost-based router computes a cost for each wire path, and the cost is based on: (1) the manhattan wire distance: (2) the layers in which the wire runs; and (3) any overlap the wire has with soft obstacles (e.g., other wires, etc.); and (4) an estimated cost to the target. Cost computation is reduced by considering only obstacles within the layer in which a lane is run. The number of paths determined for a wire route is reduced by pruning possible paths based on the placement of obstacles within the integrated circuit.

Abstract: A method and apparatus for datapath placement of irregular logic, while still allowing control of wire lengths. The method and apparatus allow use of a objective, called a directed placement objective, that causes a logic gate to be placed at or near a coordinate, such as an input or output pin connected to the gate.

Abstract: A method for power net analysis of integrated circuits is provided. A circuit simulator determines current values for integrated circuit devices at specified supply voltages. A power net simulator uses the current values to calculate characteristics of the power net. The characteristics include voltage drop, current density and ground bounce. A layout representation of the power net is shown on a computer display along with the user-specified characteristics.

Abstract: A method of and system for inserting test points within an integrated circuit design. According to the present invention, test points are inserted early in the electronic design process and prior to logic synthesis such that the problem of design constraint violation can be avoided. One embodiment of the present invention includes the computer implemented steps of receiving an unmapped netlist of an integrated circuit design, and receiving from an external source, data that indicates the location and the desired functionality of the test point to be inserted. Thereafter, the present invention inserts a generic test point circuit at the indicated location and generates a modified unmapped netlist. Subsequently, the present invention performs a logic synthesis process on the modified unmapped netlist where the generic test point circuit is degenerated into an actual test point circuit for performing the desired functionality.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.

Abstract: A simulation architecture and method having four major steps. Firstly, an input circuit description to be simulated is compiled into an initial circuit compilation as follows. The input circuit description is translated into an initial register transfer level (RTL) network representation comprised of sequential and/or combinational objects. Next, translation of the RTL network into a network of clusters is accomplished. In general, a cluster is a region of the circuit which has uniform simulation activity. The initial clustering process, by default, chooses an simulation mode for all clusters known as event-triggered cycle-based. The other possible simulation mode for a cluster, in accordance with the present invention, is oblivious-triggered cycle-based. The first major step completes with translating the network of clusters into simulatable object code which includes additional object code that generates activity data regarding each cluster during a simulation.

Abstract: A computer implemented process for automatic creation of integrated circuit (IC) geometry using a computer. The present invention includes a general unconstrained non-linear optimization method to generate coarse placement of cells on a 2-dimensional silicon chip or circuit board. In one embodiment, the coarse placer can also be used to automatically size cells, insert and size buffers, and aid in timing driven structuring of the placed circuit. The coarse placer is used in conjunction with other automatic design tools such as a detailed placer and an automatic wire router. A master objective function (MOF) is defined which evaluates a particular cell placement. A non-linear optimization process finds an assignment of values to the function variables which minimizes the MOF. The MOF is a weighted sum of functions which evaluate various metrics. An important metric for consideration is the density metric, which measures how well spread out the cells are in the placement.

Abstract: A system and method for using scalable polynomials to translate a look-up up table delay model into a memory efficient model. The system of the present invention receives an input library of predefined cells having a number of predefined look-up tables for modeling timing arcs through circuit paths of the cells. Each look-up table is referenced by two input variables (e.g., input transition rate and output load capacitance) which correspond to an output delay time. The present invention analyzes each memory inefficient look-up table and selects a polynomial form (of two variables) for representing the timing data of the look-up table. The polynomial form is selected from scalable polynomial systems (e.g., the decomposed Taylor Series and the Joint Taylor Series). The polynomial forms that are selected can have different orders (e.g., first, second, third, etc.) for the input variables.

Abstract: A method and system for generating test vectors for testing scan-based sequential circuits that contain non-scan cells using combinational ATPG techniques. The present invention includes the computer implemented step of receiving a netlist description of an integrated circuit device that comprises scan cells and non-scannable cells. Under certain conditions, some non-scan cells may exhibit sequential transparency behavior. The present invention identifies such conditions and characterizes each non-scan cell as sequentially transparent or non-transparent. Based on such characterization, the present invention transforms non-scan cells exhibiting sequential transparency behavior with transparent logic models during combinational ATPG (Automatic Test Pattern Generation) analysis. Because non-scan cells of exhibiting sequential transparency behavior are not replaced with “force-to-X” models, the fault coverage of the test patterns thus generated is significantly improved.

Abstract: A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic.

Abstract: A unique, efficient method and system for reliability simulation of a semiconductor chip design comprising millions of transistors. Specifically, the instant method starts by storing device information about a chip design as inputted. Next, by first partitioning the complex circuit of the design into numerous smaller stages, each of which confines direct current flow within its boundary, then estimating the current consumption and the relative current contribution of each transistor for each stage, the method of the present invention determines the individual currents of all power network transistors with sufficient accuracy for reliability simulation. The instant method then uses the individual transistor currents and the stored device information, including data of an accurate resistor-capacitor model of the power network, to determine the branch currents and node voltages in all interconnect wires of the power network.