Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.

Abstract: A one-transistor (1T) one-time programmable (OTP) anti-fuse bitcell is provided. The 1T OTP anti-fuse bitcell includes a gate, a diffusion region including at least two sub-regions, and a gate oxide region located between the gate and the diffusion region, the gate oxide region including a thin gate oxide region and a thick gate oxide region.

Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Abstract: The technology disclosed relates to verifying metastability for a clock domain crossing (CDC) in a circuit design. The technology disclosed may include, for a destination clock domain in the circuit design, creating a circuit graph based, at least in part, on the circuit design. The circuit graph includes start points and stop points. The start points may be data inputs, clocks, and enables of the destination clock domain. The stop points may be synchronizer outputs of the destination clock domain and a source clock domain in the circuit design. The technology disclosed may also include traversing the circuit graph to mark all graph nodes that reside in a source-destination path of the CDC. Based on the marked graph nodes, the start points, and the stop points, the technology disclosed may also include propagating destination domain qualifiers on the circuit graph within an allowed sequential depth.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for direct measurement of the capacitance of a Josephson junction. Roughly, the technique includes detecting the resonance frequency f of the junction under test, determining the DC voltage Vp across the junction under test at resonance frequency, and determining the capacitance of the junction under test in dependence upon the critical current Ic of the junction under test and the DC voltage Vp. This Abstract is not intended to limit the scope of the claims.

Abstract: Embodiments provide efficient, robust, and accurate programmatic prediction of optimized TCAD simulator system settings for future simulation executions to be performed by a TCAD simulation system.

Abstract: Some aspects of this disclosure are directed to an automated method to check electrostatic discharge (ESD) effect on a victim device. For example, some aspects of this disclosure relate to a method, including determining a probe point, in a circuit design, for determining effective resistance between the probe point and ground, where the probe point is on an ESD path of in the circuit design. The method includes determining voltage between the probe point and the ground. The method further includes comparing, by a processing device, a resistance value of the ESD path determined based a predefined electric current value at a source point and the measured voltage with a target resistance value range. The method further includes reporting a violation upon determining that the determined resistance value of the ESD path is outside the target resistance value range.

Abstract: Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include a non-superconducting structure having a hollow region. A first superconducting structure may be disposed inside the hollow region of the non-superconducting structure, and a second superconducting structure may be disposed around the non-superconducting structure outside the hollow region.

Abstract: A single flux quantum (SFQ) cell may include SFQ circuitry to implement a logic function that generates logic values of a set of outputs based on logic values of a set of inputs. The SFQ circuitry may instantaneously update logic values of the set of outputs in response to changes in logic values of the set of inputs. The SFQ circuitry may include at least one SFQ non-destructive set-reset flip-flop.

Abstract: A method is disclosed including analyzing a layout netlist including a first set of nodes against a schematic netlist including a second set of nodes. Each node of the first and second sets of nodes is assigned a matching type for identifying matching nodes between the first and second sets of nodes. The method includes determining one or more unmatched nodes between the first set of nodes and the second set of nodes based on the matching type. The method includes generating a convergence graph comprising nodes of the first set of nodes that have a corresponding matching node in the second set of nodes based on the matching type, and the one or more unmatched nodes.

Abstract: A method to report a phantom object for a structure in a power-and-ground (PG) router is disclosed. The method includes generating the structure of a PG network based on a spec received as input, identifying a violation of a design rule for the structure, and changing the structure to remove the violation of the design rule. The method further includes generating a report of the violation and the changing, generating a phantom object based on the changing, and outputting the report and the phantom object.

Abstract: Techniques and systems for solving a set of constraints are described. Binary decision diagram (BDD) learning can be applied to a proper subset of the first set of constraints to obtain a set of bit-level invariants. The set of bit-level invariants can then be used for solving the set of constraints. The set of bit-level invariants can include (1) forbidden invariants, (2) conditional invariants, and/or (3) bit-level invariants that are determined by applying BDD learning to a conjunction of constraints and range expressions. If multiple implied constraints have a common right-hand-side (RHS) expression, then BDD learning can be applied to the common RHS expression only once.

Abstract: Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.

Abstract: A system and method for providing electrical circuit design using cells with metal lines are described herein. According to one embodiment, a method includes instantiating a first parameterized cell (PCELL) into a first region of a row of an electrical circuit design. The first PCELL includes field effect transistor (FET) data representing a FET structure having a horizontal dimension and first metal track data representing a first set of adjustable parallel metal line segments extending along the horizontal dimension of the FET structure. The method also includes instantiating a second PCELL into a second region of the row adjacent to the first region. The second PCELL includes second metal track data representing a second set of adjustable parallel metal line segments. The method further includes connecting the first set of adjustable parallel metal line segments to the second set of adjustable parallel metal line segments and eliminating a connectivity short.

Abstract: A simulation application can be executed by a computer system to develop thermal maps for an electronic architectural design. The simulation application can simulate the electronic architectural design over time. The simulation application can capture electronic signals from the electronic architectural design as the electronic architectural design is being simulated over time. The simulation application can determine power consumptions of the electronic architectural design over time from the electronic signals. The simulation application can derive temperatures of the electronic architectural design over time from the power consumptions. The simulation application can map the temperatures onto an electronic circuit design real estate of the electronic architectural design to develop the thermal maps over time.

Abstract: Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.