Abstract: A tool for coupling and decoupling a connector of a cable. The tool includes a body, a bracket, and a first hook. The body has a first end portion, a second end portion opposite the first end portion, and an intermediate portion between the first end portion and the second end portion. The body has a longitudinal axis running between the first end portion and second end portion. The body also has a first surface and a second surface opposite the first surface. The bracket is disposed at the first end portion. The bracket defines a cavity configured to receive a portion of the connector, and the bracket is configured to push the connector as the tool moves in a first direction. The first hook is disposed at the intermediate portion. The first hook is configured to engage an opening defined by the connector and pull the connector as the tool moves in a second direction different than the first direction.

Abstract: A system to enable detection of the process corner of each of the P and N devices of an SRAM array (of bitcells) and of peripheral devices. This permits more focused (optimized and compensated) design of non-SRAM peripheral circuits and of read and write assist circuits for better handling of process distribution impact on circuits improving functionality and yield.

Abstract: A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.

Abstract: A circuit includes three PMOS transistors (PMOS) and three NMOS transistors (NMOS). The first PMOS has a source receiving a supply voltage and a gate receiving a first signal. The second PMOS has a source coupled to a drain of the first PMOS, a gate receiving a clock signal, and a drain generating a second signal. The third PMOS has a source receiving the supply voltage, and a drain coupled to the drain of the second PMOS. The first NMOS has a drain coupled to the drain of the second PMOS, and a gate coupled to a gate of the third PMOS. The second NMOS has a gate receiving the first signal, and a drain coupled to a source of the first NMOS. The third NMOS has a gate coupled to the gate of the third PMOS transistor, and a drain coupled to the drain of the third PMOS.

Abstract: A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.

Abstract: One or more embodiments disclosed herein pertain to a hybrid emulation system for hybrid emulation of a design under test (DUT). The system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hardware emulation system includes emulated registers for the first portion of the DUT. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. The hybrid emulation system additionally comprises a configuration file that identifies a subset of the emulated registers. The simulation system is configured with the configuration file to selectively mirror, during the hybrid emulation, the subset of the emulated registers identified by the configuration file.

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a physically unclonable function (PUF) device includes a crystalline substrate and a stack of crystalline layers on top. The stack is grown epitaxially such that lattice mismatch causes threading dislocations from the substrate to the top surface of the stack. Diodes are formed on the top surface by forming anode material on the top surface of the stack, thereby forming a diode junction with a cathode region below. A diode which includes a threading dislocation has a higher leakage current than one that does not. Circuitry connected to the diodes interrogates the array and outputs binary values indicating, for each of the diodes, whether the diode includes a threading dislocation. Such binary values can be used as the PUF of the chip. This Abstract is not intended to limit the scope of the claims.

Abstract: A method includes performing a first read operation on a memory cell of a programmed first one-time programmable (OTP) anti-fuse to determine a state of the memory cell based on a first parameter level, performing a second read operation on the memory cell of the programmed first OTP anti-fuse to determine the state of the memory cell based on a second parameter level, identifying the memory cell of the first OTP anti-fuse as an uncertain bit when the state determined during the first read operation and the state determined during the second read operation are different, and programing one or more memory cells of a second OTP anti-fuse based on a bit position of the identified uncertain bit of the first OTP anti-fuse.

Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Abstract: Route segments of a set of nets may be grouped into route groups. Terminals of the set of nets may be grouped into terminal groups. For each net in the set of nets, a net signature may be determined based on route groups associated with the net and terminal groups associated with the net. The set of nets may be grouped into net groups based on the net signatures.

Abstract: A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include creating a plurality of library (lib) cells for a directional routing layer, and determining a lib cell of the plurality of lib cells for placement of at least one repeater for the directional routing layer. The operations may also include determining a route touch region corresponding to a pin region of the lib cell through which a route is going through and inserting the at least one repeater at the route touch region. The operations may also include swapping the at least one inserted repeater to at least one target lib cell of the plurality of lib cells.

Abstract: In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet provide accurate defect coverage results.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology, roughly described, in which a semiconductor structure includes a substrate supporting a column of at least one (and preferably more than one) horizontally-oriented nanosheet transistor, each having a respective channel segment of semiconductor crystalline nanosheet material (preferably silicon or a silicon alloy) sheathed by gate stack material, wherein the channel segments have a diamond cubic crystal structure and are oriented such that the {111} planes are horizontal. Also disclosed is a method for fabricating such a structure, and a corrugated substrate that may be formed as an intermediate product. This Abstract is not intended to limit the scope of the claims.

Abstract: A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.

Abstract: A bit cell is described. In some embodiments, the bit cell comprises (1) a magnetic tunnel junction (MTJ), and (2) an access transistor circuit coupled to the MTJ, wherein the access transistor circuit comprises a negative-capacitance field-effect-transistor.

Abstract: A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.

Abstract: A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.

Abstract: Techniques and systems for automatic net grouping and routing are described. Some embodiments can determine a set of net groups by automatically grouping nets that have (1) a same pin count, (2) a pin direction type that is in a predefined set of pin direction types, and (3) a pin order type that is in a predefined set of pin order types. Next, the embodiments can generate routing guidance by performing trunk planning for each net group. The embodiments can then perform detailed routing for each net in each net group by using the routing guidance.

Abstract: Training data may be collected for each design intent in a set of design intents by identifying a set of failures that is expected to occur when the design intent is manufactured, and recording a failure mode and a location of each failure in the set of failures. Next, the training data may be used to train a machine learning model, e.g., an artificial neural network, to predict failure modes and locations of failures. The trained machine learning model, e.g., trained artificial neural network, can then be used to predict a set of failures for a given design intent. Next, for each predicted failure, a reticle enhancement technique (RET) recipe may be selected based on the failure mode of the failure, and the selected RET recipe may be applied to an area around the location of the failure.

Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.