Abstract: Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.

Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed herein is a normally-off, gallium oxide field-effect transistor. The field-effect transistor comprises a source, a source spacer, a first channel region, a second channel region, a drain spacer, and a drain. The source, the source spacer, the first channel region, the second channel region, the drain spacer, and the drain are of a first conductivity type. All the regions have the same type of doping. The field-effect transistor further includes a gate dielectric over the channel body and a gate over the gate dielectric. The first channel region has a cross-sectional area that is smaller than the second channel region.

Abstract: A two-dimensional representation of a polygon is converted to a parametric representation. A smoothing filter is applied to the parametric representation to produce corner rounding. In some embodiments, a polygon layout plus a model that specifies how much corner rounding should be applied are taken as inputs. The desired amount of rounding to the corners in the input polygons is applied and this produces a new polygon layout with corners that are properly rounded as its output. The process can be implemented so that it does not induce any pattern-size dependent bias. It also can be designed so that it does not induce line-end pullbacks. However, this feature can be turned off if line-end pullbacks are deemed appropriate for the specific application.

Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-color layer fabrication process is described. The method interpolates for simulation use between test or experimental data or descriptions to more accurately apply color differentiated parameters to the model creation and lithography simulation.

Abstract: A method for enabling user-customization of a controller design for simulation comprises accessing at least one library of individual simulation component models for controller components. The method further comprises receiving information describing an architecture of a customized controller design corresponding to a controller that controls communications between other parts of a first target system. The method additionally comprises generating a controller simulation model for the customized controller design based on the first architectural information, the controller simulation model including instances of a plurality of the simulation component models.

Abstract: Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.

Abstract: Systems, methods, and computer program embodiments are disclosed for detecting software components in a software codebase. In an embodiment, a source file containing source code may be received, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching software files. In an embodiment, the reference database may store a plurality of code signatures corresponding to software files. A list of the identified software files may be created and presented to a user.

Abstract: Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting access to the data array and at least one other instruction that accessed the data array, at least one data index for accessing the data array associated with the at least one instruction. A tag array in the cache is interfaced with a tag queue that stores one or more tag entries associated with one or more data outputs read from the data array based on accessing the data array.

Abstract: An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.

Abstract: A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.

Abstract: Gate oxide breakdown in the programming element of an OTP (One-Time Programmable) memory cell can vary widely. The resulting large variations in the conductivity of the programmed memory cells in an OTP memory cell array is used for a PUF (Physically Unclonable Function). A method of obtaining a PUF value from an OTP memory cell array is described.

Abstract: Disclosed herein are apparatus, method, and computer-readable storage device embodiments for implementing deconvolution via a set of convolutions. An embodiment includes a convolution processor that includes hardware implementing logic to perform at least one algorithm comprising a convolution algorithm. The at least one convolution processor may be further configured to perform operations including performing a first convolution and outputting a first deconvolution segment as a result of the performing the first convolution. The at least one convolution processor may be further configured to perform a second convolution and output a second deconvolution segment as a result of the performing the second convolution.

Abstract: An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.

Abstract: A memory array including a plurality of memory cells and a plurality of drivers is disclosed. The plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. Memory cells corresponding to a row of the plurality of rows may be logically grouped into a plurality of memory array segments. The plurality of drivers may be coupled to corresponding first ends of corresponding memory array segments of the plurality of memory array segments. Second ends of the corresponding memory array segments may be coupled to second ends of corresponding adjacent memory array segments of the plurality of memory array segments. The second ends of the corresponding memory array segments and the second ends of corresponding adjacent memory array segments may be coupled to corresponding wordlines of a plurality of wordlines.

Abstract: Information is received describing test response signals generated by scan cells of an integrated circuit and physical shift failures representing mismatches between the test response signals and expected test response signals of the integrated circuit. The test response signals are mapped to a subset of the scan cells associated with the physical shift failures. Fault simulation is performed for the mapped subset of the scan cells to identify physical faults located within the integrated circuit causing the physical shift failures.

Abstract: A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.

Abstract: Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.

Abstract: Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number.

Abstract: Systems and techniques are described for topography simulation of etching and/or deposition on a physical structure. The structural information can be represented using a three-dimensional (3D) voxel grid data structure. For each particle emitted by a Monte-Carlo particle emission model, a topographical modification caused by the particle can be determined by (1) calculating fluxes, (2) evaluating surface reactions, and (3) modifying the physical structure. The effect of the etching and/or deposition on a physical structure can be displayed by rendering the 3D voxel grid data structure.

Abstract: Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.