Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.

Abstract: Roughly described, a task control system for managing multi-scale simulations receives a case/task list which identifies cases to be evaluated, at least one task for each of the cases, and dependencies among the tasks. A module allocates available processor cores to at least some of the tasks, constrained by the dependencies, and initiates execution of the tasks on allocated cores. A module, in response to completion of a particular one of the tasks, determines whether or not the result of the task warrants stopping or pruning tasks, and if so, then terminates or prunes one or more of the uncompleted tasks in the case/task list. A module also re-allocates available processor cores to pending not-yet-executing tasks in accordance with time required to complete the tasks and constrained by the dependencies, and initiates execution of the tasks on allocated cores.

Abstract: Techniques and systems for improving wafer contrast by manipulating reflective extreme ultraviolet (EUV) mask absorber are described. Some embodiment disclosed herein provide for EUV absorber material, which transmits some EUV illumination, to suppress the printing of sub-resolution assist features (SRAFs) while making the SRAFs closer in size to the printed feature by thinning the SRAF absorber thickness from the nominal mask absorber thickness in the bright-field mask case. In the dark-field mask case, a layer of absorber material is left in the SRAF trenches to prevent SRAF printing.

Abstract: We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.

Abstract: The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on a plurality of injected faults and existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.

Abstract: Disclosed herein are system, method, and computer-readable storage device embodiments for implementing automated root-cause analysis for static verification. An embodiment includes a system with memory and processor(s) configured to receive a report comprising violations and debug fields, and accept a selection of a seed debug field from among the plurality of debug fields. Clone violations may be generated by calculating an overlay of a given violation of the violations and a seed debug field, yielding possible values for a subset of debug fields. A clone violation may be created for a combination of the at least two second debug fields, populating a projection matrix, which may be used to map violations and clone violations to corresponding numerical values in the projection matrix and determine a violation cluster based on the mapping having corresponding numerical values and score(s) satisfying a threshold, via ML. Clustering may further be used to generate visualizations.

Abstract: Techniques and systems for optimizing a logic network are described. Some embodiments automatically identify scenarios where Boolean methods are best driven by truth tables, binary decision diagrams (BDDs) or satisfiability (SAT). Some embodiments use circuit partitioning techniques that are based on hash-tables and topological sorting, and that are capable of grouping nodes with high simplification likelihood and still are able to efficiently scale to large circuits. Some embodiments feature a generalized resubstitution framework based on computing, and implementing, the Boolean difference between two nodes. Some embodiments include enhancements to (i) gradient-based and-inverter-graph (AIG) optimization, (ii) heterogeneous elimination for kerneling, and (iii) revisitation of maximum set of permissible functions (MSPF) computation with BDDs.

Abstract: Methods and computer readable media for software modeling. The method comprises accessing one or more software execution traces describing execution times of tasks within software executed on a target platform. The method also comprises generating a workload model of the software based on the one or more software execution traces of the software executed on the target platform. The workload model describes tasks of the software and workloads on the target platform associated with the tasks of the software.

Abstract: Techniques and systems for test case selection and ordering with covert minimum set cover for functional qualification are described. Some embodiments can determine a first set of test cases by, iteratively, identifying a set of faults that is covered by a smallest set of test cases, determining whether or not a test case that covers a fault is able to detect the fault, and selecting and adding a test case to the first set of test cases. Next, the embodiments can execute a minimum set cover process on the first set of test cases by using coverage scores for test cases in the first set of test cases for ranking.

Abstract: A system including a user interface, a memory, and a processor configured to perform operations stored in the memory is disclosed. The operations may include receiving an application specification including an application algorithm, and extracting from the application algorithm a first and a second node. The first node may include a first component of the application algorithm, and the second node may include a second component of the application algorithm that may be different from the first component. The operations may include analyzing execution dependency of the first node on the second node. The analyzing execution dependency may include analyzing computational requirements, bandwidth requirements, and input trigger requirements of the first node and the second node based on parallelism of available resources.

Abstract: Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The thread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.

Abstract: Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. As a first step, the microprocessor receives an instruction indicating a process that requires data from one or more source registers. Instead of automatically retrieving the data from the register file, which is a costly process, the microprocessor may read the scoreboard to determine whether the needed data can be more cost-effectively retrieved from the re-order buffer, retire queue, or result busses. Therefore, the microprocessor can avoid costly data retrieval procedures. Additionally, the scoreboard implementation enables the microprocessor to handle limited out-of-order instructions, which improves overall performance of the microprocessor.

Abstract: Techniques and systems for capturing and using routing intent in an integrated circuit (IC) design are described. Some embodiments use a graphical user interface (GUI) to capture routing intent for a net, wherein the routing intent includes a set of circuit objects associated with the net, a routing pattern, and optionally a set of user-provided attribute values. Next, the embodiments provide the routing intent to a router, wherein the router uses the routing intent to route the net.

Abstract: A non-volatile memory system includes an array of bit cells arranged in rows and columns and configured to store bits of data, a reference bit cell, a plurality of bit lines connectable to the bit cells in the array and connecting to the reference bit cell, and a bit line controller. The bit line controller comprises a plurality of sense amps connected to the bit cells by the bit lines. The bit line controller determines the contents of the bit cells based on times tcell compared to a time tref, where tcell is the time required for a current Icell generated by one of the bit cells to raise a voltage Vsense of one of the sense amps by an amount ?V, and tref is the time required for a current Iref generated by the reference bit cell to raise the voltage Vsense of another one of the sense amps by the same ?V. ?V increases monotonically as a function of Iref.

Abstract: The disclosure relates to a method, computer program product or data processing system for performing graph-based static timing analysis, GBA, of an integrated circuit design having a set of timing paths. The method comprises identifying a subset of the set of timing paths and performing path-based analysis, PBA, of the subset of timing paths to determine at least one PBA timing parameter for each timing path of the subset of timing paths. The method further comprises determining at least one optimized GBA timing parameter for at least one timing path of the subset of timing paths by minimizing a function that is based on a difference between the at least one optimized GBA timing parameter and the at least one PBA timing parameter of the at least one timing path.

Abstract: Systems and techniques are described for providing guidance to an equivalence checker when a design contains retimed registers. Some embodiments can perform at least a register retiming optimization on a first design to obtain a second design. Next, the embodiments can determine one or more codes to provide guidance for connecting the set/clear inputs of the retimed registers. The first design, the second design, and the one or more codes can then be provided to an equivalence checker, wherein providing the one or more codes to the equivalence checker reduces an amount of computation required by the equivalence checker to determine functional equivalence between the first design and the second design.

Abstract: A method for ciphering protected content communicated between a first device and a plurality of devices over a plurality of channels comprises performing authentication between the first device and each of the plurality of devices to create two or more shared key and initialization vector pairs allowing the ciphering of the protected content; generating a key stream for each of the channels based on a selected one of the two or more of shared key and initialization vector pairs; maintaining a buffer for each channel, each of the buffer containing the key stream generated for the corresponding channel; and ciphering data incoming on a selected channel using the selected key stream from the buffer corresponding to the selected channel.

Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

Abstract: A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer.

Abstract: An emulator emulating a DUT emulates a clock generator for generating clock signals of the DUT with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock parameter with a jitter value randomly selected from the jitter range of the clock signal. When a system fast clock cycle starts, the emulator determines the lowest value from the generated jitter clock values. The emulator outputs an edge on clock signal having the lowest jitter clock value. The emulator generates a new jitter clock value for each clock signal and the process repeats during the next system fast clock cycle.