Patents Assigned to Synopsys, Inc.
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Patent number: 10810339Abstract: A method of determining dimensional changes of features in a mask involves calculating a spacing to be used between adjacent unit cells, correcting a unit cell surrounded by replicas of the same unit cell at the calculated spacing for optical proximity effects, arraying the proximity corrected unit cell at the calculated spacing, and dividing the array of unit cells into templates. Each template frames a portion of the array of unit cells, and locations of the unit cells in each framed template are shifted relative to locations of the unit cells in other framed templates. Critical dimensions for features in the unit cell are determined within each template, and the critical dimensions determined across the template are used to obtain shift variances of each feature. A dimensional change is determined for a feature based on the shift variance for that feature.Type: GrantFiled: December 26, 2017Date of Patent: October 20, 2020Assignee: Synopsys, Inc.Inventor: David Howard Ziger
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Publication number: 20200327932Abstract: A pseudo-dual-port memory (PDPM) is disclosed that includes a first memory array bank and a second memory array bank of a plurality of memory array banks. The PDPM also includes parallel pin control logic circuitry configured to perform operations including taking a clock signal, a memory enable signal for a first port, a memory enable signal for a second port, a parallel pin control signal, and address signals for the first and the second memory array banks as inputs and generating a first internal clock and a second internal clock for performing operations corresponding to the first and the second memory array banks at the first port and the second port. A total number of memory array banks may be up to eight memory array banks and each including either a six-transistors (6-T) SRAM bit-cell or an eight-transistors (8-T) SRAM bit-cell in static random access memory architecture.Type: ApplicationFiled: April 9, 2020Publication date: October 15, 2020Applicant: Synopsys, Inc.Inventors: Praveen Kumar VERMA, Rohan MAKWANA
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Patent number: 10802566Abstract: A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.Type: GrantFiled: July 6, 2018Date of Patent: October 13, 2020Assignee: Synopsys, Inc.Inventors: Andrew Chung Chun Lam, Davit Petrosyan, Dino A. Toffolon, Morten Christiansen
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Patent number: 10803000Abstract: Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.Type: GrantFiled: December 3, 2018Date of Patent: October 13, 2020Assignee: Synopsys, Inc.Inventor: Jun Zhu
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Patent number: 10791203Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.Type: GrantFiled: October 26, 2017Date of Patent: September 29, 2020Assignee: Synopsys, Inc.Inventors: Prasad Chalasani, Venkata N. S. N. Rao, Majid Jalali Far
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Patent number: 10789398Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.Type: GrantFiled: August 23, 2017Date of Patent: September 29, 2020Assignee: Synopsys, Inc.Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
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Publication number: 20200302103Abstract: A hybrid electronic system including an emulator side including a processor and a first clock, a simulated side including one or more models to simulate one or more prototypes and a second clock, a first interface to the emulator side, and a second interface to the simulated side is disclosed. The processor is configured to determine using the first interface a first amount of time corresponding to an amount of time advanced on the emulator side by the first clock. The processor is configured to determine using the second interface a second amount of time corresponding to an amount of time advanced on the simulated side by the second clock, and set a value of a clock frequency of the second clock based on an initial value of the clock frequency of the second clock and a ratio of the first amount of time to the second amount of time.Type: ApplicationFiled: March 18, 2020Publication date: September 24, 2020Applicant: Synopsys, Inc.Inventors: Cedric BABLED, Sylvain Bayon DE NOYER
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Patent number: 10783301Abstract: A system receives a circuit description and measures of intrinsic delay, intrinsic delay variation, transition time and transition time variation for each stage and determines stage delay variation of each stage. The system receives a circuit description and derate factors and determines an intrinsic delay standard deviation and a correlation coefficient. The system determines a stage delay variation of each stage based on the determined factors. The system receives parameters describing an asymmetric distribution of delay values and generates a normal distribution of delay values. The system receives measures of nominal transition time at an output and input of a wire, and transition time variation at the input of the wire and determines a transition time variation at the output of the wire. The system receives measures of an Elmore delay and a nominal delay of the wire and determines a delay variation at the output of the wire.Type: GrantFiled: March 5, 2019Date of Patent: September 22, 2020Assignee: Synopsys, Inc.Inventors: Duc Huynh, Jiayong Le, Ayhan Mutlu, Peivand Tehrani
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Patent number: 10783311Abstract: A DRC tool optimized for analyzing early-stage (“dirty”) IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.Type: GrantFiled: October 27, 2017Date of Patent: September 22, 2020Assignee: Synopsys, Inc.Inventor: John R. Studders
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Patent number: 10775836Abstract: A method and system for cycle accurate data transfer between skewed source synchronous clocks is envisaged. The procedure starts through reset. On reset, both the write and read address registers are set to point to location 0. Source clock is stopped to disable active clock edges to both write and read address registers during the reset procedure. The source clock is subsequently started to deliver active edges w both write and read address registers. On every active source clock edge, data is pushed into the data register based on the location pointed by write address resister. On every skewed active clock edge, data is read from the data register based on the address pointed by read address register. Due to the delayed nature of clock reaching the read address register, write address register increments first and stores data into the data register.Type: GrantFiled: June 14, 2016Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Gyan Prakash, Nidhir Kumar
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Patent number: 10776560Abstract: A system for evaluating candidate materials for fabrication of integrated circuits includes a data processor coupled to a memory. Roughly described, the data processor is configured to: calculate and write to a first database, for each of a plurality of candidate materials, values for each property in a set of intermediate properties; calculate and write to a second database, values for a selected target property for various combinations of values for the intermediate properties and values describing candidate environments; and for a particular candidate material and a particular environment in combination, determine values for the intermediate properties for the candidate material by reference to the first database, and determine the value of the target property for the candidate material by querying the second database with, in combination, (1) the determined intermediate property values of the candidate material and (2) a value or values describing the particular environment.Type: GrantFiled: November 21, 2019Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Victor Moroz, Stephen Lee Smith, Yong-Seog Oh, Michael C. Shaughnessy-Culver, Jie Liu, Terry Sylvan Kam-Chiu Ma
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Patent number: 10776552Abstract: An integrated circuit design tool for modeling resistance of an interconnect specifies a structure of the interconnect in a data structure in memory in or accessible by the computer system using 3D coordinate system. For each of a plurality of volume elements in the specified structure, the tool specifies a location and one of first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length ?.Type: GrantFiled: November 27, 2017Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Victor Moroz, Ibrahim Avci, Shuqing Li, Philippe Roussel, Ivan Ciofi
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Patent number: 10777288Abstract: A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.Type: GrantFiled: August 7, 2019Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventor: Wlodek Kurjanowicz
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Patent number: 10777638Abstract: Roughly described, an integrated circuit device includes a semiconductor having an overall length. In successively adjacent longitudinal sequence, the semiconductor includes first, second and third lengths all having a same first conductivity type. One end of the longitudinal sequence (the end adjacent to the first length) can be referred to a source end of the sequence, and the other end (adjacent to the third length) can be referred to as a drain end. Overlying the second length is a first gate conductor, which defines a first body region. Overlying a cascode portion of the third length is a second gate conductor, which defines a second body region. The second gate conductor preferably is longitudinally continuous with the first gate conductor, but if not, then the two are connected together by other conductors. The first body region is recessed relative to the first and third lengths of the semiconductor.Type: GrantFiled: January 3, 2019Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Nelson de Almeida Braga, Rimvydas Mickevicius
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Patent number: 10776539Abstract: A method for simulating an epitaxial process in a body having a crystal lattice structure. Roughly described, an enlarged version of the crystal lattice structure is formed, having a lattice constant increased by a lattice enlargement factor N>1. The subject fabrication process is simulated by a Lattice Kinetic Monte Carlo algorithm in which various factors have been scaled in accordance with N. The simulation speed increases by a factor around N3, without significantly degrading the accuracy of the resulting simulated structure. The simulated epitaxial process can later be performed on a physical crystalline body.Type: GrantFiled: December 1, 2017Date of Patent: September 15, 2020Assignee: Synopsys, Inc.Inventor: Ignacio Martin-Bragado
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Patent number: 10769339Abstract: An improved local modeling function for estimating band-to-band tunneling currents RBBT in nanodevices and other low-voltage circuit elements during TCAD simulation, the model being represented by the equation: R B ? B ? T = - B ? ? F ? ? = exp ? ( - F 0 ? F ? ) ? g where terms B, F, F0 and ? correspond to conventional terms used in Hurkx-based equations, and the term g is an exponential factor determined by the equation: g = ( F - F 1 F 1 ) 1 . 5 where the term F1 is the built-in electric field at a selected cell/point determined by the equation: F 1 = max ? ( F ˜ 1 , C ? 2 ? q ? E g ? N n ? e ? t ? ) where {tilde over (F)}1 is the built-in electric field at zero bias, q is fundamental electronic charge, C is a fitting parameter, Eg is bandgap, Nnet is doping concentration, and E is dielectric constant.Type: GrantFiled: August 8, 2019Date of Patent: September 8, 2020Assignee: Synopsys, Inc.Inventors: Hiu Yung Wong, Rimvydas Mickevicius
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Patent number: 10769347Abstract: A Physical Fault Analysis (PFA) outcome prediction tool utilizes previously-generated evaluation data and associated PFA outcome data to generate a Bayesian Generalized Linear Model (BGLM), and then utilizes the BGLM to generate a PFA outcome prediction for newly-submitted evaluation data that operably characterizes measured operating characteristics of an IC chip that is being developed. The BGLM generation methodology by utilizing a Generalized Linear Model (GLM) in a Bayesian framework to form a hierarchical model representing the evaluation data and associated PFA outcome data as a linear combination. The PFA outcome prediction includes a credible interval of a posterior distribution that effectively represents a cross-sectional portion of the BGLM corresponding to the newly-submitted evaluation data.Type: GrantFiled: April 29, 2019Date of Patent: September 8, 2020Assignee: Synopsys, Inc.Inventor: Christopher W. Schuermyer
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Patent number: 10769329Abstract: A retention model includes a sequential block including two flip-flop/latch elements and a signal routing circuit having a network of alternative signal paths controlled by path control signals, which are generated by a retention controller block. The signal routing circuit enters a default operating mode when the signal path control signals are de-asserted, whereby the retention model implements a standard flip-flop/latch functionality in response to generic UPF signals applied to the model's generic input nodes, thereby facilitating RTL simulation of the retention model using a Verilog original always command. A selected retention strategy is implemented by modifying a retention controller block to assert a selected combination of path control signals, whereby the retention model may be implemented during UPF simulation using a map_retention_cell command.Type: GrantFiled: April 3, 2019Date of Patent: September 8, 2020Assignee: Synopsys, Inc.Inventors: Harsh Chilwal, Stephen T. Scherr, Todd M. Buzan
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Patent number: 10763895Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.Type: GrantFiled: June 4, 2018Date of Patent: September 1, 2020Assignee: Synopsys, Inc.Inventors: Venugopal Santhanam, Lokesh Kabra
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Patent number: 10762262Abstract: A constraint solver utilizes a modified relaxation process to generate multiple different stimulus stream arrays that comply with multi-dimensional (e.g., 2D or 3D) constraints. First, an array is generated including rows and columns of randomly generated test vector values. During a first revision phase, the array is modified to comply with first-dimension constraints (e.g., selected test vector values are changed in non-compliant rows until every row complies with all row constraints). A second revision phase is then performed in multiple cycles, where each cycle includes identifying a current element having a greatest impact on non-compliance of the array on second-dimension (e.g., column and/or diagonal) constraints, and revising the current element's test vector value in a way that both minimizes the non-compliance, and also maintains compliance of the array with the first-dimension constraints.Type: GrantFiled: October 3, 2018Date of Patent: September 1, 2020Assignee: Synopsys, Inc.Inventors: In Ho Moon, Qiang Qiang, Dhiraj Goswami