Abstract: A method of forming a DRAM capacitor structure featuring increased surface area, has been developed. The method features a polysilicon top plate structure located overlying an array comprised of individual polysilicon storage node structures. Each polysilicon storage node structure is comprised with tall, vertical features, and additional surface area is obtained via removal of butted insulator layer from a first group of surfaces of the storage node structures. Insulator layer remains butted to a second group of storage node structure surfaces to prevent collapse of the tall, vertical features of the storage node structures during subsequent processing sequences.

Abstract: The invention provides a method for etching silicon nitride selective to titanium silicide and fabricating multi-level contact openings on a quartermicron device using a two step etch process. The process begins by providing a substrate having thereover a silicon nitride hard mask at one level and a titanium silicide layer at another level wherein the silicon nitride hard mask and the titanium silicide region have an oxide layer thereover. In a first etch step, the oxide layer is patterned to form a first contact opening and a second contact opening. The first contact opening stops on the silicon nitride hard mask and the second contact opening stops on the titanium silicide region. In a second etch step the silicon nitride hard mask is etched through in the first contact opening using an etch selective to titanium silicide. The etch comprises CH2F2 and O2 at a ratio of CH2F2 to O2 of between about 2 and 4.

Abstract: A new split gate structure is disclosed with improved programming efficiency. A silicon region, extending to the surface of a semiconductor substrate, has parallel source/drain regions and electrical connecting regions disposed over the source/drain region. A multiplicity of structures is situated between source drain regions. Each structure is composed of two tower structures and intervening oxide layers. A floating gate tower, in which a gate oxide layer separates a floating gate from said silicon region and an insulating layer separates said floating gate from a top gate, with a nitride layer disposed over the top gate. And a selected gate tower in which a silicon pedestal is in intimate electrical contact with said silicon region and said silicon pedestal is separated from a selected gate by an insulating layer.

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground.

Abstract: A multi-step HDP deposition and sputtering process for void-free filling of high aspect ratio trenches and for trenches having stepped cross-sectional profiles. The method is particularly applicable to filling trenches formed in triply layered substrates comprising a silicon layer, an oxide layer and a nitride layer, wherein the nitride layer has been pulled back from the edge of the trench opening and forms a step. The method allows the void-free filling of such a trench without damaging the nitride layer in the process. Briefly, the essence of the method is the formation of deposited layers on the sidewalls of the trench wherein the first layer is deposited with a high deposition to sputtering ratio (D/S>10) and low bias power to form a thin layer, with no overhang, that is capable of protecting the nitride layer during subsequent deposition and sputtering steps.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

Abstract: Disclosed are structures and a method to increase the power dissipation of an output pad of an integrated circuit during electrostatic discharge (ESD) by preventing ESD current from flowing through resistive means between that output pad and an internal circuit. By splitting the active region and thereby creating a bipolar transistor which connects directly to the output pad, the resistive means is shunted when the bipolar transistor together with an already existing parasitic bipolar transistor conduct during ESD. Current flow in the resistive means is therefore eliminated and with it damaging power dissipation.

Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.

Abstract: A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction, and an integrated circuit having formed therein the gap filling sandwich composite dielectric layer construction. To practice the method, there is first provided a substrate having formed thereover a patterned layer. There is then formed upon the patterned layer a first conformal dielectric layer through a first plasma enhanced chemical vapor deposition (PECVD) method employing a first radio frequency power optimized primarily to limit plasma induced damage to the substrate and the patterned layer. The first radio frequency power is also optimized secondarily to limit moisture permeation through the first conformal dielectric layer. There is then formed upon the first conformal dielectric layer a gap filling dielectric layer.

Abstract: Novel capacitor top electrodes auto-self-aligned to bit-line regions is achieved with improved process yields. A first insulating layer is formed over the FETs, and a second insulating layer is deposited. Openings are etched for capacitors, and a novel photomask and etching are used to recess the second insulator. A first conducting layer is deposited for bottom electrodes, and a second photoresist is used to remove the first conducting layer on the top surfaces of the second insulating layer. A thin dielectric layer is deposited, and a second conducting layer is deposited, and polished back to form novel auto-self-aligned top electrodes to the second insulating layer for bit-line contact openings. This increases overlay margins, and the recessing of the second insulating layer in the first openings prevents polish-back damage to the bottom electrodes.

Abstract: A new method to form flash memory devices in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A first film is formed comprising a first oxide layer overlying the substrate and a floating gate layer overlying the first oxide layer. A second film is formed comprising a second oxide layer overlying the first film, a control gate layer overlying the second oxide layer, and an insulating layer overlying the control gate layer. The first and second films are patterned to form stacked gates comprising floating gates and control gates. Ions are implanted into the substrate between the stacked gates to form source and drain regions. A third oxide layer is then formed on the sidewalls of the stacked gates. A plug layer is then deposited overlying the substrate and the stacked gates and filling spaces between the stacked gates.

Abstract: A method of forming a bump structure, comprising the following steps. A structure having an exposed first conductive structure is provided. A first photoresist layer is formed over the structure and the exposed first conductive structure. A second capping photoresist layer is formed over the first photoresist layer. The first and second photoresist layers being comprised of different photoresist materials. The first and second photoresist layers are patterned to form an opening through the first and second photoresist layers and over the first conductive structure. The second capping photoresist layer prevents excessive formation of first photoresist layer residue during processing. A second conductive structure is formed within the opening. The first and second patterned photoresist layers are stripped. The second conductive structure is reflowed to form the bump structure.

Abstract: A method of fabricating a planarized metal structure comprising the following steps. A structure is provided. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having an opening formed therein and exposing at least a portion of the structure. A first-metal layer is formed over the patterned dielectric layer filling the opening. The first-metal layer including at least a doped metal portion adjacent the patterned dielectric layer. The doped metal portion being doped with a second-metal. The structure is annealed to form a second-metal oxide layer adjacent the patterned dielectric layer. The first-metal layer and the second-metal oxide layer are planarized using only a electropolishing process to remove the excess of the first-metal layer and the second-metal oxide layer from over the patterned dielectric layer and leaving a planarized metal structure within the opening.

Abstract: A method for forming an ultra-thin (between about 15 to 20 Angstroms), silicon dioxide gate insulator layer, featuring a process sequence which widens the process window of the thermal oxidation procedure, and improves the quality of the ultra-thin silicon dioxide gate insulator layer, has been developed. After a series of wet clean procedures applied to a semiconductor substrate, a high temperature anneal procedure is performed in an inert ambient. The high temperature anneal removes organic, as well as inorganic material not removed during the wet clean procedures, and also removes native oxide formed during these same wet clean procedures. The removal of these materials allow the use of longer thermal oxidation times still resulting in silicon dioxide thickness equal to counterparts formed using shorter oxidation times, which were not subjected to the pre-oxidation high temperature anneal procedure.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract: A new level-shifting circuit is achieved comprising: a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor, the second cascaded switch comprises a second NMOS transistor and a second zero threshold NMOS transistor, and the cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.

Abstract: An improved and new process for photoresist stripping for use during fabrication of semiconductor integrated circuits, which use porous low-k dielectric materials, such as OSG or HSQ, as the interlevel and intra-level insulating layers, has been developed. Photoresist stripping in microwave or rf generated plasmas in gaseous mixtures of NH3 and CO takes place without attack or damage to underlying layers of OSG or HSQ. Optimum results are obtained when the ratio of CO to NH3 is between about 0.8 and 1.2.

Abstract: A new method to form a SRAM memory cell in an integrated circuit device is achieved. The method comprises providing a bi-stable flip-flop cell having a data storage node and a data bar storage node. A first capacitor is formed coupled to the data bar storage node, and a second capacitor is formed coupled to the data storage node. The first and second capacitors comprise a first conductor layer overlying a second conductor layer with a dielectric layer therebetween. One of the first and second conductor layers is coupled to ground. A new SRAM device is disclosed.

Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Abstract: CVD dielectric materials are generally preferred for anti-reflection coatings because their optical properties can be varied both by controlling composition and by suitable surface treatment. In prior art films of this type it can be difficult to control both the refractive index and the extinction coefficient simultaneously. The present invention shows how optical properties can be tailored to meet a range of predetermined values by depositing each dielectric anti-reflection coating as a series of sub-coatings. After each sub-coating has been deposited it is subjected to surface treatment through exposure to a gaseous plasma, thereby forming an interface layer which provides a wider window for fine tuning RI and K values. Generally the finished film will comprise 3-5 of these sub-coatings. Software simulation is used to determine the precise composition for each sub-layer as well as the optical properties of the DARC film.