Abstract: A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device, has been developed. A first embodiment of this invention features a buried oxide region formed in a silicon alloy layer, via thermal oxidation procedures. A first portion of the strained silicon layer, protected during the thermal oxidation procedure, overlays the silicon alloy layer while a second portion of the strained silicon layer overlays the buried oxide region. A second embodiment of this invention features an isotropic dry etch procedure used to form an isotropic opening in the silicon alloy layer, with the opening laterally extending under a portion of the strained silicon layer.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provided, containing a p-type region. An n-type photodiode region is formed within the p-type region. A field oxide isolation region is then formed which extends beyond the p-type region and also covers the p-type region except for an active region and an overlap part of the n-type photodiode region. An n-channel MOSFET is fabricated in the active region with one of the source/drain regions of the MOSFET extending over the overlap part of the n-type photodiode region. A blanket transparent insulating layer is then deposited.

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.

Abstract: A process for fabricating an alternate fin type capacitor structure, used to increase capacitor surface area has been developed. The process features the formation of fin shaped, storage node structures, located in fin type capacitor openings, which are in turn defined in a group of composite insulator layers. A first fin type capacitor opening is formed by selectively creating lateral recesses in first type insulator layers, exposed in a first capacitor opening in the composite insulator layers, while an adjacent, second fin type capacitor opening is formed by selectively creating lateral recesses in second type insulator components, exposed in a second capacitor opening located in the same composite insulator layers. Portions of the lateral recesses in the first and second fin type capacitor openings overlay, allowing intertwined or alternate, storage node structures to be realized, thus reducing the space needed for the capacitor structure.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method of clearing photoresist on a wafer edge, including the following steps. A wafer having a upper exposed conductive layer is provided. The wafer having a center, an edge and a ring-shaped area proximate the wafer edge. A photoresist layer is formed upon the exposed conductive layer. The photoresist layer is removed from within the ring-shaped area by a rinse process to expose the conductive layer within the ring-shaped area. An oxygen diffusion barrier layer is formed over the photoresist layer.

Abstract: A method of early and effective detection of defects in a metal patterning process is described. A test keys structure is provided comprising a plurality of test keys in scribe lines of a control monitor wafer wherein more than 300 test keys are formed on a control monitor wafer and wherein each of the plurality of test keys has an area of at least 106 &mgr;m2. A metal layer is deposited on the control monitor wafer. A dielectric layer is deposited overlying the metal layer. Thereafter, the control monitor wafer is tested using the plurality of test keys.

Abstract: A method of forming a thin silicon dioxide gate dielectric layer comprised with a nitrided silicon dioxide component, obtained via a plasma nitrogen procedure performed to a base silicon dioxide layer, has been developed. The silicon dioxide gate dielectric layer, comprised with a top portion of nitrided silicon dioxide, allows lower leakage currents to be realized when compared to non-nitrided silicon dioxide counterparts. To prevent nitrogen ions or radicals from penetrating the base silicon dioxide layer during the plasma nitrogen procedure, silicon oxynitride components are formed in the base silicon dioxide layer either during the growth procedures using N2O, NO or N2O/NO as reactants, or via a post growth anneal procedure, using an anneal ambient comprised of either N2O, NO, or N2O/NO.

Abstract: A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.

Abstract: A method is provided for forming multi-layer spacer (MLS) for flash EEPROM devices. A composite tetraethyl orthosilicate-silicon nitride (TEOS/Si3N4) layer is deposited over the floating gate and anisotropically etched to form the MLS. The resulting MLS is better controlled dimensionally with the attendant advantage, therefore, of better definition of gate and channel lengths in the memory cell for more predictable and better programming and erase performance of EEPROMs.

Abstract: The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.

Abstract: A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.

Abstract: A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

Abstract: A new method is provided for the creation of a protective layer over a glass substrate, the glass substrate has a first and a second surface. Under a first embodiment of the invention, a second surface of the glass panel is first coated with a layer of TiN. A first layer of amorphous silicon (A—Si) is deposited over the second surface of the glass panel. A second layer of amorphous silicon (A—Si) is deposited over the layer of TiN. A layer of photoresist is next deposited over the surface of the second layer of A—Si. The first layer of A—Si is removed from the second surface of the glass panel after which the layer of photoresist is removed. Under a second embodiment of the invention, the first and the second surface of the glass panel are coated with a first and a second layer of TiN. A layer of amorphous silicon (A—Si) is deposited over the second layer of TiN. A layer of photoresist is deposited over the layer of A—Si.

Abstract: A high performance 1T RAM cell in a system-on-a-chip is formed using an asymmetric LDD structure that improves pass gate performance and storage node junction leakage. The asymmetric LDD structure is formed using selective ion implantation of the core and I/O LDDs. The node junctions are both pocket implant-free and source/drain implant-free. Further, silicide formation is avoided within the storage node junctions by forming nearly merged sidewall spacers within the node junctions and by forming optional blocking portions over the nearly merged sidewall spacers.

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.

Abstract: A method for making DRAM devices having reduced parasitic capacitance between closely spaced capacitors is achieved. After forming FETs for the memory cells and bit lines having bit-line contacts, a planar insulating layer is formed having an etch-stop layer thereon. Contact openings are etched in the insulating layer and are filled with polysilicon to make contact to capacitor node contact plugs. A relatively thick insulating layer having a low dielectric constant (k) is deposited, and an array of recesses are etched over the node contact plugs for crown-shaped capacitors. A polysilicon layer and an interelectrode dielectric layer are formed in the array of recesses, and another polysilicon layer is patterned to complete the crown capacitors. The low-k insulator between adjacent capacitors reduces the parasitic capacitance and improves data retention of DRAM cells. Alternatively, higher density of memory cells can be formed without increasing parasitic capacitance.

Abstract: Low K dielectrics, such as porous silica, present a problem during damascene processing in that the trench floor tends to be rough, thus requiring a thicker than desired barrier layer. This problem has been overcome by fully covering the trench floor with a layer of a flowable material following which an etchant is provided that etches both the trench and flowable materials at approximately the same rate. Using this etchant, the trench floor is then uniformly etched until only a small amount of flowable material remains. After removal of any and all remaining flowable material, it is found that the roughness at the trench floor has been reduced by a factor of about 3-5. This allows a barrier layer of normal thickness to be used during the standard copper damascene process without danger of copper leakage. The process is particularly well suited for use with porous silica dielectrics having a dielectric constant less than about 2.5.

Abstract: A new method is provided for the interconnection of bit lines in the test structure. The invention provides for the creation of a cross comb bit line design in the test structure which allows for the detection and identification of diagonal or horizontal bridging between two identifiable capacitors of DRAM structures.