Abstract: A method is provided to form a split-gate flash memory not susceptible to inadvertent reverse tunneling during programming. This is accomplished by forming a silicon nitride spacer on the negatively tapered walls of the floating gate of the cell which serves as a barrier to reverse tunneling. The negatively tapered walls, in contrast to vertical walls, is disclosed to provide a geometry better suited for forming thicker spacers around the floating gate, which in turn serve to act as a more robust barrier to reverse tunneling. Furthermore, it is shown that the method requires fewer steps than practiced in prior art.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A process for forming a buried stack capacitor structure in a recessed region of a shallow trench isolation (STI) region, has been developed. The process features a unique sequence of procedures eliminating possible polysilicon stringers or residuals which if left remaining would result in leakage or shorts between conductive elements. The unique sequence of procedures include: deposition of a silicon oxide layer on the polysilicon layer from which the storage node structure will be defined from; photoresist plugs used to protect the portions of the silicon oxide and the underlying polysilicon layer located in the recessed region, during definition of the polysilicon storage node structure; and definition of the polysilicon storage node structure via a wet etch procedure, using the silicon oxide layer for protection of the underlying polysilicon storage node structure.

Abstract: A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

Abstract: A self-adjusting prediction system that provides for the transmission and storage of push lots of work. It uses an adaptive control algorithm in it's methodology to improve Automated Material Handling Systems (AMHS) transmissions. The method of prediction is greatly enchanted to reduce overall cycle time, incorrect transmission of work lots, and idle manufacturing tools. It provides real-time updating that enables a complex manufacturing Fab to process work with optimum movement between tools.

Abstract: A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET.

Abstract: A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration of this invention places the tungsten plug, on a portion of a metal silicide layer, in a region directly overlying the dopant interface, (N type-P type regions), in the polysilicon dual gate structure. A second iteration of this invention places the tungsten plug directly on the dopant interface of the polysilicon dual gate structure, with the tungsten plug structure formed in a borderless opening, in an insulator layer. The use of the tungsten plug allows a less resistive current path through the polysilicon dual gate structure, when compared to counterparts fabricated without the tungsten plug structure, in which a more resistive current path, through a diode present at dopant interface, exists.

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively.

Abstract: A new method is provided to monitor and to prevent IMD oxide irregularities such as IMD oxide cracks. A monitoring pattern is inserted in the test line of the fabrication substrate to monitor the strength of the created layer of IMD oxide. Variations in the characteristics of the created layer of IMD oxide can in this manner be detected. In addition, design rules are provided that are aimed at avoiding layers of IMD oxide that have proven or are known to be particularly prone to the occurrence of IMD oxide cracks.

Abstract: A process for fabricating CMOS devices, featuring a channel region comprised with a strained SiGe layer, has been developed. The process features the selective growth of a composite silicon layer on the top surface of N well and P well regions. The composite silicon layer is comprised of a thin, strained SiGe layer sandwiched between selectively grown, undoped silicon layers. The content of Ge in the SiGe layer, between about 20 to 40 weight percent, allows enhanced carrier mobility to exist without creation of silicon defects. A thin silicon dioxide gate insulator is thermally grown from a top portion of the selectively grown silicon layer, located overlying the selectively grown SiGe layer.

Abstract: A new method is provided for the removal of liner oxide from the surface of a gate electrode during the creation of the gate electrode. A layer of gate oxide is formed over the surface of a substrate, a layer of gate electrode such as polyimide is deposited over the layer of gate oxide. The gate electrode and the layer of gate oxide are patterned. A layer of liner oxide is deposited, gate spacers are formed over the liner oxide, exposing surfaces of the liner oxide. The created structure is nitrided by a plasma stream containing N2/H2, reducing the etch rate of the exposed liner oxide. The liner oxide is then removed by applying a wet etch, contact regions to the gate electrode are salicided.

Abstract: A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of a heavily doped P+ contact area residing in an N well region on a P substrate and electrically connected to the input pad of active integrated field effect transistor devices. NFET devices with floating gates and drains to reduce capacitance are located in the substrate near the N-well. The NFET source elements as well as the substrate are connected to ground. The NFETs are isolated from the N-well and associate P+ contact area by shallow trench isolation (STI) structures that reduce the NFET drain to substrate and N-well to substrate junction boundary area with a subsequent reduction in the junction capacitance. A voltage pulse from an ESD event will cause the SCR structure and associated parasitic bipolar transistors to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.

Abstract: A method and a solution for preparing SEM samples comprising low-K dielectric materials. The process begins by providing a SEM sample comprising low-K dielectric material and silicon oxide material. A solution is formed for preparing (staining and etching) the SEM sample by adding NH4F (s) to a solution comprising CH3COOH having a concentration of about 98% at a ratio of about 1 g NH4F (s):20 ml CH3COOH, then stirring until the NH4F (s) is thoroughly dissolved. Alternatively, the NH4F (s) can be added to a solution comprising HNO3 having a concentration of about 70% and CH3COOH having a concentration of about 98%, with a volume ratio of about 15 ml HNO3:20 ml CH3COOH. The NH4F (s) is added at a ratio of about 1 g NH4F (s):35 ml CH3COOH and HNO3, and stirred until the NH4F (s) is thoroughly dissolved. The SEM sample is then etched in this solution for about 3 seconds, whereby the low-K dielectric material and silicon oxide material have similar etch rates with good selectivity to metals.

Abstract: A new design is provided for the heat spreader of a semiconductor package. Grooves are provided in a surface of the heat spreader, subdividing the heat spreader for purposes of stress distribution into four or more sections. This division of the heat spreader results in a reduction of the mechanical and thermal stress that is introduced by the heat spreader into the device package. Mechanical and heat stress, using conventional heat spreader designs, has a negative, stress induced, effect on the semiconductor die, on the contact points (bump joints) of the semiconductor die and on the solder ball connections of the package.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide.

Abstract: In magnetic RAMs a particular memory cell is selected when it is at the intersection of a row and a column of half-selected cells. When data is written into the selected cell, the associated magnetic field can sometimes disturb a neighboring half-selected cell. This restricts the current range available for programming cells. The present invention solves this problem by using two bit lines. One end of the memory cell is connected to a first bit line, in a similar manner to the prior art. However, the programming line does not extend across the full width of the array, being instead connected to a second bit line immediately after it has passed directly across the memory cell. Orthogonal to the two bit lines is a word line whose role is to activate/deactivate transistors associated with the selected cell. Both 1T1R and 2T1R versions of the invention are described.

Abstract: This invention provides a circuit and a method for discharging a high voltage to ground level from a circuit node especially in intergrated circuits. The invention relates to a high voltage discharge circuit which prevents semiconductor latch-up and prevents semiconductor damage during the discharge process. In addition, the discharge process takes a short amount of time. A feedback mechanism from the drains of the FETs through inverters back to gate #2 of the dual-gated FETs causes the individual drains of series connected FETs to discharge rapidly. The discharge mechanism of this invention minimizes the voltage times current power and therefore protects the integrated devices from damage.