Abstract: A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.

Abstract: In a method of optimizing a lithography model in a lithography simulation, a mask is formed in accordance with a given layout, a wafer is printed using the mask, a pattern formed on the printed wafer is measured, a wafer pattern is simulated using a wafer edge bias table and the given mask layout, a difference between the simulated wafer pattern and the measured pattern is obtained, and the wafer edge table is adjusted according to the difference.

Abstract: A method for fabricating a photomask is provided. The method includes several operations. A photomask substrate, having a chip region and a peripheral region adjacent to the chip region, is received. A reference pattern is formed by emitting one first radiation shot and a first beta pattern is formed by emitting a plurality of second radiation shots in the peripheral region. The plurality of second radiation shots are emitted along a first direction. A roughness of a boundary of the first beta pattern along the first direction is compared to a roughness of a boundary of the reference pattern along the first direction from a top view perspective. An alignment of the plurality of second radiation shots is adjusted if a result of the comparison exceeds a tolerance, or the photomask is formed. A photomask structure thereof and a method for manufacturing a semiconductor are also provided.

Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device with target sputtering, including a chamber for accommodating a consumable target, a target accumulative consumption counter, wherein the target accumulative consumption counter provides a signal correlated to an amount of the consumable target being consumed, and a power supply communicates with the consumable target counter, wherein the power supply provides a power output according to the signal.

Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an insulating layer over a substrate, a gate stack formed in the insulating layer, and an insulating capping layer formed in the insulating layer to cover the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack. The source/drain contact structure has a sidewall that is in direct contact with a sidewall of the insulating capping layer, and an upper surface that is substantially level with an upper surface of the insulating capping layer and an upper surface of the insulating layer. In addition, the semiconductor device structure includes a first via structure above and electrically connected to the gate stack and a second via structure above and electrically connected to the source/drain contact structure.

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a shield layer is formed over the first conductive layer forming a bilayer structure, a capping layer is formed over the shield layer, a first annealing operation is performed after the capping layer is formed, the capping layer is removed after the first annealing operation, and a gate electrode layer is formed after the capping layer is removed.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: A method of manufacturing a semiconductor device is disclosed. In the method, a metallic layer is formed over a substrate, the metallic layer is surface-treated with an alkaline solution, and a bottom anti-reflective coating (BARC) layer is formed on the surface-treated metallic layer.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate and an oxidation region formed on the semiconductive substrate. The oxidation region includes a stage with a first width along a horizontal direction. The semiconductor structure further includes a fin formed on a top surface of the stage. A method for forming the semiconductor structure is also provided.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

Abstract: A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.

Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

Abstract: In some embodiments, the present disclosure relates to a wafer trimming and cleaning apparatus, which includes a blade that is configured to trim a damaged edge portion of a wafer, thereby defining a new sidewall of the wafer. The wafer trimming and cleaning apparatus further includes water nozzles and an air jet nozzle. The water nozzles are configured to apply deionized water to the new sidewall of the wafer to remove contaminant particles generated by the blade. The air jet nozzle is configured to apply pressurized gas to a first top surface area of the wafer to remove the contaminant particles generated by the blade. The first top surface area overlies the new sidewall of the wafer.

Abstract: A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.