Abstract: A semiconductor device includes a plurality of connectors and at least one insulating layer disposed over a semiconductor substrate. A molding layer extends around the plurality of connectors. A sidewall of the molding layer that is closest to a scribe line is offset from the scribe line.

Abstract: A method includes providing first and second wafers; forming a first device layer in a top portion of the first wafer; forming a second device layer in a top portion of the second wafer; forming a first groove in the first device layer; forming a second groove in the second device layer; bonding the first and second wafers together after at least one of the first and second grooves is formed; and dicing the bonded first and second wafers by a cutting process, wherein the cutting process cuts through the first and second grooves.

Abstract: A substrate table is provided. The substrate table includes a main body configured to support a substrate thereon. The substrate table further includes a number of vacuum channels provided in the main body and respectively formed with a vacuum opening on a surface of the main body. The vacuum channels are configured to apply a vacuum to the substrate. The vacuum channels are distributed throughout the main body and arranged in a grid pattern.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: A device comprises a first metal structure, a dielectric structure, a dielectric residue, and a second metal structure. The dielectric structure is over the first metal structure. The dielectric structure has a stepped sidewall structure. The stepped sidewall structure comprises a lower sidewall and an upper sidewall laterally set back from the lower sidewall. The dielectric residue is embedded in a recessed region in the lower sidewall of the stepped sidewall structure of the dielectric structure. The second metal structure extends through the dielectric structure to the first metal structure.

Abstract: A method includes positioning an end effector at a height lower than a height of a wafer. The end effector is moved to a position under the wafer. A wafer backside property of the wafer is detected by using a sensor on the end effector. The wafer backside property is analyzed to obtain an analysis result.

Abstract: The present disclosure describes a method for forming a capping layer within a low-k layer of a metallization layer to prevent damage to the low-k layer from subsequent processing operations. The method includes forming, on a substrate, a metallization layer having conductive structures in a low-k dielectric. The method further includes forming a capping layer on the conductive structures, where forming the capping layer includes exposing the metallization layer to a first plasma process to form a nitrogen-rich protective layer below a top surface of the low-k dielectric, releasing a precursor on the metallization layer to cover top surfaces of the conductive structures with precursor molecules, and treating the precursor molecules with a second plasma process to dissociate the precursor molecules and form the capping layer. Additionally, the method includes forming an etch stop layer to cover the capping layer and top surfaces of the low-k dielectric.

Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.

Abstract: Integrated optical devices and methods of forming the same are disclosed. A method of forming an integrated optical device includes the following steps. A substrate is provided. The substrate includes, from bottom to top, a first semiconductor layer, an insulating layer and a second semiconductor layer. The second semiconductor layer is patterned to form a waveguide pattern. A surface smoothing treatment is performed to the waveguide pattern until a surface roughness Rz of the waveguide pattern is equal to or less than a desired value. A cladding layer is formed over the waveguide pattern.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.

Abstract: A method for processing a substrate by using fluid flowing through a particle detector is provided. The particle detector is utilized to detect nano-particles contained in fluid. The particle detector includes a substrate and a pair of sensing electrodes disposed on the substrate. The substrate includes nano-pores, wherein the pore size of the nano-pores is greater than the particle size of the nano-particles, allowing the nano-particles contained in the fluid passing through the nano-pores. The pair of sensing electrodes are positioned adjacent to at least one of the nano-pores.

Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.

Abstract: A method of manufacturing an integrated circuit device includes: doping a substrate with a first type dopant to form a well region; forming a first semiconductor fin and a second semiconductor fin wider than the first semiconductor fin over the well region; forming a first source/drain region of a second type dopant on the first semiconductor fin, the second type dopant is of a different conductivity type than the first type dopant; forming a second source/drain region of the first type dopant on the second semiconductor fin.

Abstract: The present disclosure describes a storage device including a top panel, a bottom panel, a back panel, a front panel, and two side panels configured to form an enclosed volume. The storage device further includes multiple slots disposed at inner surfaces of the two side panels and configured to hold a substrate, a gas diffuser disposed at an inner surface of the back panel and configured to provide a purge gas to the enclosed volume, an isolation gas device disposed on an inner surface of the top panel and adjacent to a top portion of the front panel, and an isolation gas line configured to connect the isolation gas device to the gas diffuser. The isolation gas device is configured to inject the purge gas into a front portion of the storage device and in a direction from the top panel toward the bottom panel.

Abstract: A method disclosed includes the following operations as below: forming at least one capacitor between multiple interposing conductors and multiple gates; and forming multiple interposing connectors connected to the interposing conductors. One of the interposing conductors is interposed between two adjacent gates of the gates. In a plain view, the interposing connectors are separate from the gates.

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.