Abstract: An image sensor may include a polydimethylsiloxane (PDMS) layer that is subwavelength, hydrophobic, and/or antireflective. The PDMS layer may be fabricated to include a surface having a plurality of nanostructures (e.g., an array of convex protuberances and/or an array of concave recesses). The nanostructures may be formed through the use of a porous anodic aluminum oxide (AAO) template that uses a plurality of nanopores to form the array of convex protuberances and/or the array of concave recesses. The nanostructures may each have a respective width that is less than the wavelength of incident light that is to be collected by the image sensor to increase light absorption by increasing the angle of incidence for which the image sensor is capable of collecting incident light. This may increase the quantum efficiency of the image sensor and may increase the sensitivity of the image sensor.

Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.

Abstract: A semiconductor device includes a device layer, a semiconductor layer, a sensor element, a dielectric layer, a color filter layer, and a micro-lens. The semiconductor layer is over the device layer. The semiconductor layer has a plurality of microstructures thereon. Each of the microstructures has a substantially triangular cross-section. The sensor element is under the microstructures of the semiconductor layer and is configured to sense incident light. The dielectric layer is over the microstructures of the semiconductor layer. The color filter layer is over the dielectric layer. The micro-lens is over the color filter layer.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

Abstract: The present disclosure relates to a CMOS image sensor. The image sensor comprises a pixel region comprising a photodiode disposed within a substrate. A deep trench isolation (DTI) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. A pair of shallow trench isolation (STI) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. A pixel device is disposed at the front-side of the substrate directly overlying the DTI ring. The pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.

Abstract: Integrated circuit (“IC”) layouts are disclosed for improving performance of memory arrays, such as static random access memory (“SRAM”). An exemplary IC device includes an SRAM cell and an interconnect structure electrically coupled to the SRAM cell. The interconnect structure includes a first metal layer electrically coupled to the SRAM cell that includes a bit line, a first voltage line having a first voltage, a word line landing pad, and a second voltage line having a second voltage that is different than the first voltage. The first voltage line is adjacent the bit line. The word line landing pad is adjacent the first voltage line. The second voltage line is adjacent the word line landing pad. A second metal layer is disposed over the first metal layer. The second metal layer includes a word line that is electrically coupled to the word line landing pad.

Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Abstract: A magnetoresistive random access memory (MRAM) cell includes a bar-type magnetic tunneling junction (MTJ), where the antiferromagnetic layer, the free layer, the barrier layer, and the reference layer have substantially aligned sidewalls. A spacer is against the sidewall of each of the antiferromagnetic layer, the free layer, the barrier layer, and the reference layer. A bar-type MTJ is manufactured from a single element of a pattern for isolated MTJs for MRAM cells. A barrier layer of a bar-type MTJ has a larger area than column-type MTJs, leading to extended MRAM cell lifetime because the barrier layer has a lower tunneling current density across the barrier layer.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.

Abstract: A method includes following steps. A photoresist-coated substrate is received to an extreme ultraviolet (EUV) tool. An EUV radiation is directed from a radiation source onto the photoresist-coated substrate, wherein the EUV radiation is generated by an excitation laser hitting a plurality of target droplets ejected from a first droplet generator. The first droplet generator is replaced with a second droplet generator at a temperature not lower than about 150° C.

Abstract: A gate dielectric structure is formed over a channel structure. One or more work function (WF) metal layers of a metal gate are formed over the gate dielectric structure. The one or more WF metal layers are treated with a fluorine-containing material. One or more processes are performed to cause fluorine from the fluorine-containing material to diffuse at least partially into the gate dielectric structure.

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: A fuse structure includes first and second transistors where each of the first and the second transistors has a source terminal, a drain terminal, and a gate terminal; a first source/drain contact disposed on the source terminal of the first transistor; a second source/drain contact disposed on the drain terminal of the second transistor; an insulator disposed laterally between the first and the second source/drain contacts; a source/drain contact via disposed on the first source/drain contact; and a program line connected to the source/drain contact via, wherein a width of the insulator is configured such that a programming potential applied across the source/drain contact via and the drain terminal of the second transistor causes the insulator to break down.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Abstract: A semiconductor structure includes an n-type epitaxial source/drain feature (NEPI) and a p-type epitaxial source/drain feature (PEPI) over a substrate, wherein a top surface of the NEPI is lower than a top surface of the PEPI. The semiconductor structure further includes a metal compound feature disposed on the top surface of the NEPI and the top surface of the PEPI. The metal compound feature extends continuously from the top surface of the NEPI to the top surface of the PEPI. The semiconductor structure further includes a contact feature disposed on the metal compound feature and a via structure disposed over the contact feature.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.