Abstract: A bonded optical device is disclosed. The bonded optical device can include a first optical element, a second optical element, and an optical pathway. The first optical element has a first array of optical emitters configured to emit light of a first color. The first optical element is bonded to at least one processor element, the at least one processor element including active circuitry configured to control operation of the first optical element. The second optical element has a second array of optical emitters configured to emit light of a second color different from the first color. The second optical element is bonded to the at least one processor element. The optical pathway is optically coupled with the first and second optical elements. The optical pathway is configured to transmit a superposition of light from the first and second optical emitters to an optical output to be viewed by users.

Abstract: A cooling system comprising a cooling circuit connecting a heat exchanger and a heat load. The cooling system comprising a first velocity fuse upstream of the heat exchanger or heat load and a second velocity fuse or valve downstream of the heat exchanger or heat load. The heat exchanger or heat load is dynamically isolated from the rest of the cooling system by the first velocity fuse or the second velocity fuse in response to a velocity of a flow of cooling fluid exceeding a respective velocity setting of the first velocity fuse or the second velocity fuse.

Abstract: The present disclosure is drawn to, among other things, a method of managing a magnetoresistive memory (MRAM) device. In some aspects, the method includes receiving a configuration bit from a write mode configuration register. In response to determining the configuration bit is a first value, the MRAM device is operated in a NOR emulation mode. In response to determining the configuration bit is a second value, the MRAM device is operated in a persistent memory mode.

Abstract: A chip grading method includes: electrical performance test data of at least one wafer is acquired; chips on the wafer are grouped by using a clustering analysis algorithm according to the electrical performance test data of the wafer, so as to obtain a group to which each of the chips belongs, and a clustering model is established; for each group, a feature set of each group is extracted by using a Principal Component Analysis (PCA) algorithm, and a PCA model is established; the chips in each group are ranked according to scores of the chips in the group with respect to each of a preset number of features in the feature set, so as to obtain a level to which each of the chips belongs; and grading results of the chips are obtained according to both the group and the level to which each chip belongs.

Abstract: In the specification and drawings a method of securing a voting transaction is described and shown that includes initiating a voting transaction; verifying the identity of a voter; generating a passcode by the voting system; transmitting the passcode from the voting system to the voter over the telecommunication network; entering the passcode into a voting station; making one or more voting selections by the voter; transmitting the one or more voting selections from the voting station to the voting system over the telecommunication network; transmitting the passcode from the voting station to the voting system over the telecommunication network; verifying the authenticity of the passcode by the voting system; and declining to include the one or more voting selections in a vote count unless the passcode transmitted to the voting system by the voting station is verified authentic.

Abstract: An electrical panel assembly comprising at least one circuit breaker and a mounted low-profile circuit breaker lock-out assembly is disclosed. The circuit breaker lock-out assembly includes a first and second mount. The first mount is for mounting to a first end of a circuit breaker housing wall adjacent a circuit breaker switch lever and includes an outward projection having a through-hole. The second mount is for mounting to a second end of the circuit breaker housing wall and includes a pivotally attached arm that is rotatable between an unlocked and locked position in which the arm is aligned with the outward projection allowing a lock to be inserted through the projection through-hole and a corresponding hole in the arm. The arm is shaped to receive the circuit breaker switch lever and hold the lever immobile when the arm is in the locked position and the lock is inserted.

Abstract: A discharge unit is connected to a power pad, a ground pad, and an I/O pad, and can discharge an electrostatic charge when an electrostatic pulse appears on any of the power pad, the ground pad, and the I/O pad. The discharge unit includes a first discharge unit and a second discharge unit, the first discharge unit is connected to the second discharge unit, the power pad, and the I/O pad, and the second discharge unit is connected to the ground pad and the I/O pad. The first discharge unit and/or the second discharge unit can discharge electrostatic charges on different pads, respectively.

Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

Abstract: A TSV test structure includes: a plurality of TSV groups, each TSV group comprising electrically connected TSVs; a power supply circuit, connected with the TSV groups and configured to provide a first voltage or a second voltage to each TSV group; a control circuit, connected to the power supply circuit and configured to provide a first control signal and a second control signal to the power supply circuit, wherein the power supply circuit outputs the first voltage to at least one TSV group according to the first control signal, and outputs the second voltage to at least one TSV group according to the second control signal; and a readout circuit, electrically connected with the plurality of TSV groups and configured to read electrical signals on the plurality of TSV groups after the control circuit provides the first control signal and the second control signal.

Abstract: A footwear system includes a sensorized insole and a charger. The sensorized insole has an insole bulk having a foot-facing upper surface. A sensor is embedded in the insole bulk for measuring a parameter of a user's foot, a battery is embedded in the insole bulk for providing energy to the sensor, and a receiver pod is embedded in the insole bulk and is spaced from the foot-facing upper surface for wirelessly receiving energy and providing energy to the battery. The charger provides energy to the receiver pod, and includes a cable for connecting to an energy source, and a transmitter pod electrically connected to the cable for receiving energy from the cable and wirelessly transmitting energy to the receiver pod. The transmitter pod is positionable against the foot-facing upper surface to wirelessly provide energy to the receiver pod through the insole bulk.

Abstract: A semiconductor structure includes at least one transistor. The transistor includes a channel, a gate, a source, and a drain. The channel includes a first material layer and a second material layer arranged around the first material layer. Resistivity of the first material layer is greater than a first preset value, and resistivity of the second material layer is less than a second preset value, the first preset value being greater than the second preset value. The gate covers at least one side of the channel. The source and the drain are at two ends of an extension direction of the channel.

Abstract: A semiconductor structure includes a substrate, a barrier layer covering the substrate, first adjustment layers, and first contact structures. The substrate includes multiple spaced Active Areas (AAs). The AAs include first contact areas. The barrier layer is provided with multiple spaced first contact holes, each of which penetrates through the barrier layer and extends into the substrate to expose a respective one of the first contact areas. Each of the first adjustment layers is on a sidewall of a respective one of the first contact holes. Each of the first contact structures fills a respective region enclosed by the first adjustment layer and the first contact area. A method for manufacturing a semiconductor structure is also provided.

Abstract: To remedy short term data retention issues, a non-volatile memory performs a multi-pass programming process to program data into a set of non-volatile memory cells and identifies non-volatile memory cells that experienced downward threshold voltage drift after a first pass of the multi-pass programming process and prior to a final pass of the multi-pass programming process. The final pass of the multi-pass programming process comprises programming non-volatile memory cells not identified to have experienced the downward threshold voltage drift to a set of final target threshold voltages and purposefully overprogramming non-volatile memory cells identified to have experienced the downward threshold voltage drift to threshold voltages greater than respective final target threshold voltages by one or more offsets.

Abstract: A tray for holding a plurality of storage drives includes a sheet of material formed to include: a plurality of tray sidewalls, each having a top edge and a bottom edge; a plurality of tray ends walls arranged relative to the plurality of tray sidewalls to define a plurality of corner regions, each tray end wall having a top edge and a bottom edge; at least one side extension included in each of the tray sidewalls; at least one corner extension included in a corner region; and a tray top spanning the tray sidewalls and the tray ends walls. The tray top includes a pair of top-side surfaces that extend inward from the top edge of a respective one of the tray sidewalls, and a central slotted structure spanning the top-side surfaces. The central slotted structure forms a plurality of slots, each configured to receive one of the plurality of storage drives.

Abstract: After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n? buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n? buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n? buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

Abstract: Methods and systems are provided for generating a dynamic lighting scenario over a scenario timeline using solid-state light emitters. The method can include a step of providing a plurality of lighting reference points in the dynamic lighting scenario, each lighting reference point having an associated reference illumination state to be achieved at a corresponding reference moment of the scenario timeline. The method can also include a step of determining a plurality of sets of reference control parameters for the solid-state light emitters, each set of reference control parameters for producing the reference illumination state associated to a corresponding one of the plurality of lighting reference points. The method can also include driving the solid-state light emitters based on the plurality of reference control parameters to generate the dynamic lighting scenario.

Abstract: A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a physical layer and communication channels. The hardware system includes a first interface coupled to the plurality of hardware processors. The first interface is configured to be coupled to a software simulator comprising a physics model configured to provide model parameters based on modeled communication hardware and a temporal modeling scenario. A second interface is coupled to the plurality of hardware processors. The second interface is configured to be coupled to simulated or real nodes for sending and receiving network data to and from the nodes. The hardware processors are configured to model effects of the physical layer and communication channels on the network data.

Abstract: A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.

Abstract: A radiography system for use on a pipe traversing robot, including a mechanism configured to automatically adjust the position(s) of a radiation source and/or an imager thereof based on a diameter of the pipe. Another radiography system including a computer vision system configured to process radiography imagery to define a measured interface between the pipe and insulation surrounding the pipe, and a control system configured to automatically adjust a position(s) of a radiation source and/or an imager thereof based on a location of or non-presence of the measured interface in the radiography imagery. A computer vision system for detecting potential anomalies in a pipe's surface. A fail safe mechanism configured to prevent a robot from falling off a pipe while allowing the robot to traverse obstacles extending from or tangential to the pipe. A robot having one or more fail safe mechanisms configured to be selectably extended and retracted.

Abstract: Devices and techniques are generally described for pre-caching of speech processing feature data. In various examples, first data indicating source data is received from a first speech processing component. The source data may be used to generate first feature data. In various examples, a first request to process first input data is received. A second speech processing component may generate the source data during processing of the first input data. The first feature data may be generated using the source data. The first feature data may be sent to the first speech processing component. In some examples, the first speech processing component may store the first feature data in a first cache local to the first speech processing component.