Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11757815
    Abstract: One embodiment provides a hub of a collecting device that receives messages from entities. The messages are formatted in a message structure that is dependent upon an entity sending the message. The hub analyzes each of the received messages by identifying, from the message structure, information corresponding to an interest of the collecting entity, and discarding information of the message not of interest to the collecting entity. The analysis is agnostic with respect to the entity sending the message and the message structure of the message. The hub performs an action based upon the information corresponding to an interest of the collecting entity.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: September 12, 2023
    Assignee: TELETRACKING TECHNOLOGIES, INC.
    Inventors: Michael Coen, Sunil Nagireddy, Raghu Ramesh
  • Patent number: 11758467
    Abstract: A mobile application capable of superseding default phone settings to give priority to calls and messages based on a preconfigured list, as well as broadcast messages and calls within a defined group of members.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: September 12, 2023
    Assignee: GLOLINK TECHNOLOGIES INC.
    Inventors: Kalaiselvan Muniyan, Kalaiarasi Kalaiselvan, Ridhikaanth Kalaiselvan, Kaushik Kalaiselvan
  • Patent number: 11751642
    Abstract: A buckle device capable of displaying a locked state includes a main body unit, a latch unit, a fastening unit, an electromagnetic unit, and a control unit. The main body unit includes a main body and the latch unit includes a detachable tongue element. The fastening unit includes a bolt body interfering with the tongue element. The electromagnetic unit includes an electromagnetic module and an electromagnetic rod. The electromagnetic module controls the electromagnetic rod to interfere with the bolt body. The control unit includes a control module, a display module and a magnetic rod detection module for detecting the position of the electromagnetic rod. The control unit receives detection information of the magnetic bolt detection module and controls the display module to display a current state according to the position of the at least one electromagnetic rod.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: September 12, 2023
    Assignee: BROGENT TECHNOLOGIES INC.
    Inventors: Shih-Kuang Chiu, Chia-Wei Yeh, Juei-Tsung Chen
  • Patent number: 11757451
    Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: September 12, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Dimitri Houssameddine, Syed M. Alam, Sanjeev Aggarwal
  • Patent number: 11754711
    Abstract: A device includes a controller with a processor and memory with instructions for controlling power to a light source such that the light source emits a frequency-modulated continuous light beam that, over time, includes an up region, a down region, and a flat region. The up region includes increasing a frequency of the continuous light beam, the down region includes decreasing the frequency of the continuous light beam, and the flat region includes maintaining the frequency of the continuous light beam at a constant frequency.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 12, 2023
    Assignee: LUMINAR TECHNOLOGIES, INC.
    Inventors: Daniel J. Klemme, Pierre Asselin, Zoran Jandric
  • Patent number: 11754619
    Abstract: The present disclosure provides a probing apparatus for semiconductor devices using pressurized fluid to control the testing conditions. The probing apparatus includes a housing configured to define a testing chamber; a device holder positioned on the housing and configured to hold and support at least one device under test; a platen positioned on the housing and configured to retain at least one probe; a card holder positioned on the platen and configured to hold a probe card including the probe; and at least one flow line positioned in the card holder. The flow line is configured to flow a fluid therein to adjust the temperature of the device under test.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: September 12, 2023
    Assignee: STAR TECHNOLOGIES, INC.
    Inventors: Choon Leong Lou, Chen-Wen Pan, Jung-Chieh Liu
  • Patent number: 11756212
    Abstract: Systems and methods are provided to evaluate moving objects undergoing periodic motion through the screening of a video recording of such objects in motion for frequency peaks in the spectral data, and to determine spatially where these frequencies occur in the scene depicted in the video recording, wherein a frequency spectrum is created for a subset of pixels or virtual pixels and a composite frequency spectrum table or graph is constructed of frequencies that are selected from among the larger group of frequencies represented by the frequency peaks of the spectral data.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: September 12, 2023
    Assignee: RDI TECHNOLOGIES, INC.
    Inventors: Jeffrey R. Hay, Mark William Slemp, Kenneth Ralph Piety
  • Patent number: 11755208
    Abstract: Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: September 12, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ariel Navon, Alexander Bazarsky, Ofir Pele, Daniel Joseph Linnen
  • Patent number: 11756049
    Abstract: Systems and techniques are generally described for detecting evasive terms in item listings. In some examples, a first list of terms is determined. Terms of the first list of terms may be associated with evasive listing practices. In various examples, a first embedding representing a first term in an embedding space may be determined. In some examples, the top k closest embeddings in the embedding space to the first embedding may be determined. A term associated with one of the top k embeddings may be determined. A first Levenshtein distance between the first term and the second term may be determined. A list of items associated with the second term may be determined based on the Levenshtein distance being less than a threshold distance. An alert related to the list of items may be generated.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 12, 2023
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Ravi Shankar
  • Patent number: 11756107
    Abstract: Disclosed are various embodiments for providing a unique navigation experience for a user interacting with an electronic commerce site by dynamically generating a navigation interface according to a user context for a given shopping experience. The user context associated with a user interacting with an electronic commerce site can be determined following an analysis of a variety of context factors. A navigation interface can be dynamically generated based on the user context. In some examples, navigation components within the navigation interface can be associated with different categories that the user can navigate through. The navigation components can visually indicate a level of completeness for a given category so that the user is aware of where he or she is in a given shopping experience.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 12, 2023
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: David Sigler, Feroz Abdul Kadar, Xiaoqi Shi, Wesley Lauka
  • Patent number: 11753645
    Abstract: The present disclosure relates to aptamers, polynucleotides, and nuclei acid molecules, which include a polynucleotide sequence capable of specifically binding polypeptides participating in M. hyopneumoniae infection. Also provided are methods of using nucleic acid molecules, polynucleotides and synthetic antibodies directed there against for detection, treating and neutralization of M. hyopneumoniae infection.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: September 12, 2023
    Assignee: AEROVIRUS TECHNOLOGIES INC.
    Inventors: Norman J Marchand, Thomas G Caltagirone, Albert Liao
  • Patent number: 11754107
    Abstract: A node to panel interface structure for use in a transport structure such as a vehicle is disclosed. In an aspect, the node includes a base, first and second sides protruding from the base to form a recess for receiving a panel, ports for adhesive injection and/or vacuum generation, one or more adhesive regions disposed on a surface of each side adjacent the panel, and at least one channel coupled between the first and second ports and configured to fill the adhesive regions with an adhesive, the adhesive being cured to form a node-panel interface. The node may be additively manufactured. In an exemplary embodiment, the node may use sealant features for including sealants that border and define the adhesive regions, and that may hermetically seal the region before and after adhesive injection. In another embodiment, the node may include isolation features for including isolators for inhibiting galvanic corrosion.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 12, 2023
    Assignee: DIVERGENT TECHNOLOGIES INC.
    Inventors: William David Kreig, Chukwubuikem Marcel Okoli, David Brian TenHouten, Antonio Bernerd Martinez, Kevin Robert Czinger, Broc William TenHouten
  • Patent number: 11758209
    Abstract: Systems and methods for video distribution synchronization are described herein. An example method to distribute a media stream over a distribution network to a number of devices may include determining, by one or more computer processors coupled to memory, a common master-client shared time reference Tref. Example methods may include determining a mean intermediate arrival time for first packets of a first type of the media stream, determining respective first playout times for the first packets based on the mean intermediate arrival time and the time reference Tref, associating the first packets with the respective first playout times, and distributing the media stream to the plurality of devices.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: September 12, 2023
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Per Lindgren, Ted Olsson, Anders Cedronius, Hans Insulander, Christer Bohm, Magnus Danielson
  • Patent number: 11756880
    Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: September 12, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
  • Publication number: 20230282594
    Abstract: A semiconductor wafer includes semiconductor dies and laser grooves formed in the scribe lines along the long edges of the semiconductor dies. A laser groove extends between the long edges of two adjacent semiconductor dies to encompass the corners of the two adjacent semiconductor dies. This prevents die cracking, for example during backgrind of the wafer. Moreover, the absence of laser grooves along the short edges of the semiconductor dies prevents die cracking, for example along short edges of dies overhanging empty space that are stressed during portions of the packaging process.
    Type: Application
    Filed: March 7, 2022
    Publication date: September 7, 2023
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chin-Tien Chiu, Jia Li, Dongpeng Xue, Huirong Zhang, Guocheng Zhong, Xiaohui Wang, Hua Tan
  • Publication number: 20230282517
    Abstract: In a method for forming a semiconductor device, a substrate is provided; a word line is formed in the substrate by taking a first face of the substrate as an upper surface; a connecting layer electrically connected to one end of the word line is formed in part of the substrate and on the substrate; a first conducting layer is formed on the connecting layer; and a conducting plug is formed in the substrate by taking a second face of the substrate as an upper surface. The conducting plug is electrically connected to another end of the word line and electrically connected to the first conducting layer via the word line. The first face and the second face are two faces of the substrate opposite to each other in a thickness direction of the substrate.
    Type: Application
    Filed: May 13, 2023
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: CHIH-CHENG LIU
  • Publication number: 20230284453
    Abstract: A semiconductor structure includes a gate dielectric layer and a gate located on a surface of the gate dielectric layer, in which the gate dielectric layer includes an oxide layer, a charge trapping layer and an isolation layer stacked in sequence, and the isolation layer is made of a polarization material capable of spontaneous polarization.
    Type: Application
    Filed: July 11, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wei Chang
  • Publication number: 20230280416
    Abstract: A circuit for through silicon via (TSV) detection includes a TSV to be tested, an equivalent adjustable resistor and a reverse output circuit. A first terminal of the TSV to be tested is connected to a second terminal of the equivalent adjustable resistor, and a second terminal of the TSV to be tested is grounded. An input terminal of the reverse output circuit is connected to the first terminal of the TSV to be tested. The method includes: adjusting a resistance value of the equivalent adjustable resistor to a preset first resistance value, and keeping a voltage of a first terminal of the equivalent adjustable resistor at a preset voltage value, the first resistance value is a maximum resistance value of an equivalent resistor corresponding to the TSV to be tested when the TSV to be tested is normal.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weijie CHENG, ONEGYUN NA
  • Publication number: 20230282265
    Abstract: A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.
    Type: Application
    Filed: September 30, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jixing CHEN
  • Publication number: 20230282268
    Abstract: A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.
    Type: Application
    Filed: July 2, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xianjun WU, Weibing SHANG