Abstract: Provided are p97 (melanotransferrin)-trastuzumab fusion proteins and related methods of use thereof, for instance, to facilitate delivery of trastuzumab across the blood-brain barrier (BBB) and/or improve tissue penetration of the antibody in CNS and peripheral tissues, and thereby treat and/or diagnose HER2-positive cancers, including those of the central nervous system (CNS).
Type:
Grant
Filed:
February 10, 2019
Date of Patent:
May 9, 2023
Assignee:
BIOASIS TECHNOLOGIES, INC.
Inventors:
Timothy Z. Vitalis, Reinhard Gabathuler
Abstract: Embodiments described herein may provide devices, systems, methods, and/or computer readable medium for adverse event detection and severity estimation in surgical videos. The system can train multiple models for adverse detection and severity estimation. The system can load selected models for real-time adverse event detection and severity estimation.
Type:
Grant
Filed:
February 14, 2020
Date of Patent:
May 9, 2023
Assignee:
SURGICAL SAFETY TECHNOLOGIES INC.
Inventors:
Haiqi Wei, Teodor Pantchev Grantcharov, Babak Taati, Yichen Zhang, Frank Rudzicz, Kevin Lee Yang
Abstract: A portable oxygen concentrator retrofit system and method in which an existing portable oxygen concentrator may be retrofitted to output an enriched oxygen gas at a flow rate suitable for use in a patient ventilation system without the need for an external source of compressed gas.
Abstract: A method for accessing a memory includes the following. Location information of fail bits of multiple banks is acquired, backup circuits are distributed to the target banks from the multiple banks according to the location information of the fail bits by using a repair algorithm, a predicted repair result of the target bank is acquired, the availability of the target bank is detected according to the predicted repair result of the target bank, information indicating whether bits of target partial address bits of the target banks are predicted to be valid or invalid is acquired, and then predicted partial address bits are determined from the multiple address bits according to the information of the target partial address bits of the target banks to access a memory in a partial access mode according to the predicted partial address bits.
Abstract: A parsing method includes the following: during parsing target bank, performing a row hammer operation on a logical row in target bank to determine a physical position relationship of the logical row; repeatedly performing the operation of performing the row hammer operation on the logical row in target bank to determine the physical position relationship of the logical row until all logical rows have been parsed; and determining a mapping relationship used for recording physical position relationships of multiple logical rows according to a linked list; where performing the row hammer operation on the logical row in target bank includes: acquiring a to-be-parsed logical row in target bank including multiple logical rows; performing the row hammer operation on the to-be-parsed logical row until at least one flipped logical row is obtained; and writing the at least one flipped logical row into the linked list.
Abstract: Blowing equipment (10) for doctor equipment of a fiber web machine (10) includes a distribution channel (11), the length of which corresponds essentially to the length of the doctor equipment (40). The blowing equipment (10) also includes nozzle devices (12) for directing blowing in the doctor equipment (40). The nozzle devices (12) are arranged to be adapted to a blade holder (13) that belongs to the doctor equipment (40) for establishing doctor blowing. The distribution channel (11) is adapted to be fastened to the blade holder (13). The invention also relates to doctor equipment of a fiber web machine, where the doctor equipment is equipped with blowing equipment.
Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase and perform a first error checking and correction processing, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data; perform a second ECC encoding processing on the first data on which the first error checking and correction processing has been performed, to generate a second encoded data; and choose to transmit a to-be-written data to a memory die based on a selection signal in the writing phase, where the to-be-written data is either an initial data or a second data; and choose to transmit the initial data or third data in a reading phase based on a selection signal.
Abstract: A turbofan engine has a fan portion in fluid communication with a core stream and a bypass stream of air separated by splitters disposed both upstream and downstream of the fan portion. A blade splitter (shroud) on the fan partially spans the fan blade thus separating the core and bypass streams downstream while leaving a gap upstream for communication between the flows. The communication gap expands the operational range of the fan over fans without the communication gap.
Type:
Application
Filed:
December 29, 2022
Publication date:
May 4, 2023
Applicant:
ROLLS-ROYCE NORTH AMERICAN TECHNOLOGIES INC.
Abstract: A base die is configured to receive first data and first encoded data in a writing phase, perform first error checking and correction processing, wherein the first encoded data is obtained by performing a first error correction code encoding processing on the first data, and transmit second data to a memory die in the writing phase, wherein the second data includes a first data after the first error checking and correction processing; the base die is further configured to receive the second data from the memory die in a reading phase, perform second error correction code encoding processing on the second data to generate second encoded data, and transmit third data in the reading phase, wherein the third data includes the second encoded data and the first data after the first error checking and correction processing.
Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.
Abstract: A method a for controlling a distribution sequence for a semiconductor device includes: acquiring the quantity of all chambers and an actual working duration of each radio frequency device in the machines; providing an optimal working duration of the radio frequency device to calculate an average interval; sorting all the data to form a first queue data set, and obtaining a difference between adjacent data in the first queue data set; using a difference between adjacent consecutive data as a feature value corresponding to the former or latter data in the consecutive data, and using data that does not correspond to the difference as a feature value corresponding to the data; obtaining a second queue data set and a third queue data set; and obtaining a distribution sequence of distributing N batches of wafers to all the radio frequency devices.
Abstract: A fuse structure includes a gate structure, a first electrode, a second electrode and an isolation structure. The gate structure is at least partially formed on an active area of a substrate. The first electrode is formed on the active area of the substrate and spaced apart from the gate structure. The second electrode is formed at least on a side of the gate structure. The isolation structure is formed between the active area and the second electrode.
Abstract: A method for detecting a layout of an integrated circuit includes: a finger structure is determined in the layout, the finger structure including at least one upper connection source-drain terminal and at least one upper connected via, the at least one upper connected source-drain terminal being electrically connected to an upper metal line through the at least one upper connected via; a number of the at least one upper connected source-drain terminal and a number of the at least one upper connected via are calculated; and for the finger structure, in response to the number of the at least one upper connected source-drain terminal being greater than the number of the at least one upper connected via, it is determined that the finger structure is an unqualified finger structure.
Abstract: An electrostatic protection circuit for a chip including a power supply pad and a ground pad, the electrostatic protection circuit includes: a monitoring assembly, configured to generate a trigger signal when an electrostatic pulse is present on the power supply pad; a discharge transistor connected between the power pad and the ground pad and configured to be turned on under control of the trigger signal to discharge electrostatic charges to the ground pad; and a control circuit connected to the monitoring assembly and configured to control a duration of the trigger signal generated by the monitoring assembly.
Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing on the first data and the second encoded data, and transmit a third data in the reading phase.
Abstract: A base die is configured to: receive first data in a writing phase, perform error correction code encoding processing to generate encoded data, and transmit second data to a memory die in the writing phase, wherein the second data includes the first data and the encoded data; and receive the second data from the memory die in a reading phase, perform error checking and correction processing, and transmit third data in the reading phase, wherein the third data is the first data after the error checking and correction processing.
Abstract: A board adapter device includes: a first adapter structure provided with a gold finger matched with a board of a target memory module, a second adapter structure provided with a connector matched with the gold finger, and a signal transmission structure including a first and second transmission module. The first transmission module is for connecting a data signal line, a clock signal line, an address signal line, and a control signal line of the gold finger to corresponding connecting lines of the connector. The second transmission module is configured to, when receiving a power input signal, convert the power input signal into a power output signal matched with a power supply of the target memory module, and transmit the power output signal to a power signal line of the connector.
Abstract: A base die is configured to: receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on a first sub-data to generate a second encoded data, and transmit a second data to a memory die in the writing phase; where the second data includes the first sub-data, a second sub-data, the first encoded data, and the second encoded data; the base die is further configured to: receive the second data from the memory die in a reading phase, perform first error checking and correction processing on the first sub-data and the second encoded data, and transmit a third data in the reading phase.
Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.
Abstract: A semiconductor memory device, also referred to as a solid state drive, includes thermally conductive components such as a conductive coating to draw heat away from the semiconductive package. The coating may also be electrically conductive to provide shielding from and absorption of electromagnetic interference. In examples, a semiconductor device including a substrate may be affixed to an edge connector printed circuit board with solder balls to form a solid state drive. In further examples, the substrate may be omitted, and semiconductor memory dies, a controller die and other electronic components may be directly surface mounted to an edge connector printed circuit board to form a solid state drive.
Type:
Application
Filed:
November 3, 2021
Publication date:
May 4, 2023
Applicant:
WESTERN DIGITAL TECHNOLOGIES, INC.
Inventors:
Hui Xu, Kim Lee Bock, Rama Shukla, Chong Un Tan, Yoong Tatt Chin, Shrikar Bhagath